Patent
Squid stack pulse height bias-level sensor for reciprocal quantum logic
| العنوان: | Squid stack pulse height bias-level sensor for reciprocal quantum logic |
|---|---|
| Patent Number: | 12045,692 |
| تاريخ النشر: | July 23, 2024 |
| Appl. No: | 17/736646 |
| Application Filed: | May 04, 2022 |
| مستخلص: | An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted. |
| Inventors: | Dai, Haitao O. (Ellicott City, MD, US); Nielsen, Max E. (Riverton, UT, US); Braun, Alexander Louis (Baltimore, MD, US); Dosch, Daniel George (Glen Burnie, MD, US); Pleim, Kurt (Halethorpe, MD, US); Wallace, Charles Ryan (Orlando, FL, US) |
| Assignees: | NORTHROP GRUMMAN SYSTEMS CORPORATION (Falls Church, VA, US) |
| Claim: | 1. A reciprocal quantum logic (RQL) bias-level sensor comprising: a stack of direct current superconducting quantum interference devices (DC SQUIDs) coupled to each other between a first output terminal and a second output terminal of the RQL bias level sensor, each DC SQUID in the stack comprising a superconducting loop comprising two Josephson junctions (JJs), each DC SQUID in the stack being transformer-coupled to a respective Josephson transmission line (JTL) to receive flux from an output of the respective JTL, wherein the RQL bias-level sensor is configured to output a voltage signal between the first output terminal and the second output terminal that is variable with a value of at least one bias parameter of a bias signal provided to the RQL bias-level sensor, the bias parameter being one of an AC bias amplitude or a DC bias value. |
| Claim: | 2. The RQL bias-level sensor of claim 1 , wherein the JTLs transformer-coupled to the respective DC SQUIDs are transformer-coupled to a bias signal source, configured to provide the bias signal, more strongly or more weakly than a transformer-coupling to the bias signal source of a JTL in operational RQL circuitry that is not a part of the RQL bias-level sensor. |
| Claim: | 3. The RQL bias-level sensor of claim 2 , wherein a bias tap inductor of each of the JTLs transformer-coupled to the respective DC SQUIDs is larger than a bias tap inductor of the JTL in the operational RQL circuitry, such that the JTLs transformer-coupled to the respective DC SQUIDs are each more weakly coupled to the bias signal source than the JTL in the operational RQL circuitry. |
| Claim: | 4. The RQL bias-level sensor of claim 2 , wherein: each of the JTLs transformer-coupled to the respective DC SQUIDs is more weakly coupled to the bias signal source than the JTL in the operational RQL circuitry, and the coupling strengths of the JTLs transformer-coupled to the respective DC SQUIDs are varied with respect to each other. |
| Claim: | 5. The RQL bias-level sensor of claim 4 , wherein the coupling strengths of the JTLs transformer-coupled to the respective DC SQUIDs are staged linearly. |
| Claim: | 6. The RQL bias-level sensor of claim 5 , wherein respective lower AC bias amplitude limits of respective operating ranges of the JTLs transformer-coupled to the respective DC SQUIDs are centered about a centroid of an operating range of the operational RQL circuitry. |
| Claim: | 7. The RQL bias-level sensor of claim 1 , wherein the JJs of a first of the DC SQUIDs in the stack have higher critical currents than the JJs of a second of the DC SQUIDs in the stack, and the JJs of the second of the DC SQUIDs in the stack have higher critical currents than the JJs of a third of the DC SQUIDs in the stack. |
| Claim: | 8. The RQL bias-level sensor of claim 7 , wherein the respective critical currents of the JJs of the DC SQUIDs in the stack are staged linearly. |
| Claim: | 9. The RQL bias-level sensor of claim 1 , wherein the RQL bias-level sensor is configured to measure an output amplifier output bias current provided between the first output terminal and the second output terminal. |
| Claim: | 10. The RQL bias-level sensor of claim 1 , further comprising JTL-based buffers coupled to inputs of the JTLs transformer-coupled to the respective DC SQUIDs to provide different amounts of time delay to each of the JTLs transformer-coupled to the respective DC SQUIDs, such that the voltage signal output between the first output terminal and the second output terminal comprises a series of time-staggered step functions with timing of each step function corresponding to firing of an individual one of the DC SQUIDs in the stack. |
| Claim: | 11. The RQL bias-level sensor of claim 1 , having between five and ten DC SQUIDs in the stack. |
| Claim: | 12. A system comprising first and second instances of the RQL bias-level sensor of claim 1 , an output of the first instance being coupled to a first input of bias parameter adjustment logic, an output of the second instance being coupled to a second input of the bias parameter adjustment logic, the bias parameter adjustment logic having a first output configured to command an adjustment to a bias parameter of a first clock signal provided to an RQL system, and the bias parameter adjustment logic having a second output configured to command an adjustment to a bias parameter of a second clock signal provided to the RQL system, the second clock signal being about 90° out of phase with the first clock signal. |
| Claim: | 13. The system of claim 12 , wherein the bias parameter adjustment logic is complementary metal-oxide-semiconductor (CMOS) logic located outside of a cryogenic cold space in which the first and second instances of the RQL bias-level sensor are located. |
| Claim: | 14. The system of claim 12 , wherein: the JTLs transformer-coupled to the respective DC SQUIDs in the first instance of the RQL bias-level sensor are biased by the first clock signal, the JTLs transformer-coupled to the respective DC SQUIDs in the first instance of the RQL bias-level sensor are biased by the second clock signal, the first output of the bias parameter adjustment logic is configured to command an adjustment to an AC amplitude of the first clock signal, and the second output of the bias parameter adjustment logic is configured to command an adjustment to an AC amplitude of the second clock signal. |
| Claim: | 15. The system of claim 14 , wherein the bias parameter adjustment logic further has a third input configured to provide a reference signal to which the output of the first instance and the output of the second instance are compared. |
| Claim: | 16. A reciprocal quantum logic (RQL) bias signal adjustment method comprising: driving a first RQL bias parameter sensor with a first AC clock bias signal of an RQL system; driving a second RQL bias parameter sensor with a second AC clock bias signal of the RQL system, the second AC clock bias signal being about 90° out of phase with the first AC clock bias signal; comparing the outputs of the first and second sensors; and based on the comparing the outputs of the first and second sensors, adjusting one or both of the AC amplitude of the first AC clock bias signal or the AC amplitude of the second AC clock bias signal. |
| Claim: | 17. The method of claim 16 , wherein the comparing the outputs of the first and second sensors is done by logic circuitry located outside of a cryogenic cold space in which the first and second RQL bias parameter sensors are located. |
| Claim: | 18. The method of claim 17 , wherein the comparing the outputs of the first and second sensors includes comparing the outputs of the first and second sensors to each other and comparing the comparing the outputs of each of the first and second sensors to a reference signal provided to the logic circuitry. |
| Claim: | 19. The method of claim 16 , further comprising: driving a third RQL bias parameter sensor with a third AC clock bias signal of the RQL system, the third AC clock bias signal being about 45° out of phase with the first AC clock bias signal; comparing the outputs of the first and third sensors; and based on the comparing the outputs of the first and third sensors, adjusting one or both of the phase of the first AC clock bias signal or the phase of the second AC clock bias signal. |
| Claim: | 20. The method of claim 19 , wherein the comparing the outputs of the first and third sensors is done by logic circuitry located outside of a cryogenic cold space in which the first and third RQL bias parameter sensors are located. |
| Patent References Cited: | 8464109 June 2013 Whetsel 10615783 April 2020 Powell, III et al. 20120317451 December 2012 Whetsel 20140082445 March 2014 Whetsel 20200044632 February 2020 Powell, III |
| Other References: | Strong, et al.; “A resonant metamaterial clock distribution network for superconducting logic”; Nat. Electron., Mar. 24, 2022, 171-77, vol. 5, Nature, U.S. cited by applicant Strong, et al.; “A resonant metamaterial clock distribution network for superconducting logic”; Nat. Electron., Mar. 24, 2022, 171-77, vol. 5, Nature, U.S. Figures 2-3. cited by applicant WOISR (Written Opinion & International Search Report) for corresponding PCT/US2023/017457, mailed May 2, 2024. cited by applicant Dai, et al.: “Isochronous Data Link Across a Superconducting Nb Flex Cable with 5 femtojoules per Bit”; arXiv:2109.01808v2, Oct. 2021 [retrieved on Apr. 23, 2024]. Retrieved from https://arxiv.org/abs/2109.01808v2; sections 1-2. cited by applicant Posey, et al.: “Demonstration of Superconducting Memory with Passive Transmission Line-based Reads”; In: MEMSYS 2019: Proceedings of the International Symposium on Memory Systems, Sep. 20, 2019. cited by applicant |
| Primary Examiner: | Rios Russo, Raul J |
| Attorney, Agent or Firm: | Tarolli, Sundheim, Covell & Tummino LLP |
| رقم الانضمام: | edspgr.12045692 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |