Patent
Housing for an infrared radiation micro device and method for fabricating such housing
| العنوان: | Housing for an infrared radiation micro device and method for fabricating such housing |
|---|---|
| Patent Number: | 10002,896 |
| تاريخ النشر: | June 19, 2018 |
| Appl. No: | 13/379263 |
| Application Filed: | June 21, 2010 |
| مستخلص: | Infrared radiation micro device, cover for such a device and method for its fabrication, the device comprising a substrate and a cover and an infrared radiation detecting, emitting or reflecting infrared micro unit, the infrared micro unit being arranged in a cavity defined between the substrate and the cover, the cover comprising an antireflective surface texture to enhance the transmissibility of infrared radiation, wherein a distance frame formed in an additive process on the substrate side of the cover and/or the cover side of the substrate is arranged between substrate and cover. |
| Inventors: | Reinert, Wolfgang (Neumünster, DE); Quenzer, Jochen (Itzehoe, DE); Tinnes, Sebastien (Tullins, FR); Roman, Cécile (Lans en vercors, FR) |
| Assignees: | FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V. (Munich, DE), ULIS SAS (Veurey-Voroize, FR) |
| Claim: | 1. A method of housing an infrared radiation micro unit the method having the following steps: providing a housing comprising a cover, a substrate, and a silicon distance frame, wherein the substrate is part of a substrate wafer and the cover is part of a cover wafer; masking the cover with a pattern configured to form an area with a surface texture, the surface texture provided to reduce an effective refractive index of the cover; etching the cover as patterned and creating the area with the surface texture comprising one of elevations and depressions that reduce the effective refractive index of the cover within the area; providing the silicon distance frame on a substrate side of the cover, wherein the silicon distance frame is provided by: depositing an unstructured TEOS layer on the cover comprising the surface texture, thus also covering the area of reduced effective refractive index with the unstructured TEOS layer; depositing by a CVD a silicon layer on the unstructured TEOS Layer; masking the CVD deposited silicon layer with a pattern that defines the silicon distance frame; etching the CVD deposited silicon layer to provide the silicon distance frame; removing the unstructured TEOS layer from the cover, outside the silicon distance frame, to expose the surface texture having the reduced effective refractive index; bonding of substrate and cover with the silicon distance frame being intermediate, whereby substrate, cover and distance frame form a cavity, housing the infrared radiation micro unit to provide an infrared radiation micro device on a wafer level; and wherein the cover wafer is diced and the substrate wafer is not diced, exposing the undiced substrate wafer with the diced cover wafer for electrical device characterization to a test gas atmosphere, measuring a vacuum level, thereby identifying leaking infrared radiation micro device on the undiced substrate wafer for a later rejection. |
| Claim: | 2. The method according to claim 1 , further comprising applying a getter material on the cover or the substrate. |
| Claim: | 3. The method according to claim 2 , wherein getter material is applied by an argon free evaporation process. |
| Claim: | 4. The method according to claim 1 , further comprising applying a seal frame metallization on the silicon distance frame by gold and tin electroplating. |
| Claim: | 5. The method according to claim 1 , further comprising depositing several layers of Ge—ZnS on the cover, each Ge—ZnS-layer having a different layer thickness for eliminating several wavelengths of an incident infrared radiation. |
| Claim: | 6. The method according to claim 5 , wherein the several layers are deposited on the substrate far side of the cover and being a Ge—ZnS-multilayer system. |
| Claim: | 7. The method according to claim 1 , further comprising bonding of substrates and covers with intermediate silicon distance frames, whereby each group of substrate, cover and silicon distance frame forms its own cavity, housing an individual infrared radiation micro unit. |
| Claim: | 8. The method according to claim 1 , wherein as the cover wafer is diced electrical contact pads are exposed. |
| Claim: | 9. The method according to claim 1 , wherein the substrate wafer is diced to singulate tested infrared radiation micro devices. |
| Claim: | 10. The method according to claim 1 , wherein the vacuum level is measured by detecting thermal insulation properties of the housed infrared micro units. |
| Patent References Cited: | 5450053 September 1995 Wood 6001696 December 1999 Kim et al. 6030900 February 2000 Grassi et al. 6157042 December 2000 Dodd 6228770 May 2001 Pradeep 2002/0025637 February 2002 Maeda 2002/0037626 March 2002 Muth 2004/0072384 April 2004 Cole 2004/0140570 July 2004 Higashi 2007/0170363 July 2007 Schimert et al. 2008/0277672 November 2008 Hovey et al. 2008/0283991 November 2008 Reinert 2009/0140146 June 2009 Sogawa 2012/0132522 May 2012 Foster 102008060796 May 2010 0734589 October 1996 1463120 September 2004 2065930 June 2009 61000723 January 1986 1216219 August 1989 2003149434 May 2003 2003249434 September 2003 2005067047 July 2005 2007054524 May 2007 2007069750 June 2007 |
| Other References: | XP-002550724; Database WPI Week 200343; Thomson Scientific; London, GB. cited by applicant Motamedi, M.E. et al.; Antireflection Surfaces in Silicon Using Binary Optics Technology; Applied Optics, OSA, Optical Society of America; Aug. 1, 1992; vol. 31, No. 22; pp. 4371-4376; Washington, D.C. cited by applicant Persat, Nathalie; International Search Report; Application No. PCT/EP2010/058748; dated Dec. 7, 2010; European Patent Office. cited by applicant Communication pursuant to Article 94(3) EPC; European Patent Application No. 10725764.4; dated Jun. 9, 2015; European Patent Office; Munich, Germany; see text pertaining to US 2008/277672 on last four pages of document. cited by applicant |
| Assistant Examiner: | Allen, III, Ernest |
| Primary Examiner: | Nadav, Ori |
| Attorney, Agent or Firm: | Stevens & Showalter LLP |
| رقم الانضمام: | edspgr.10002896 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |