Patent
Decision feedback equalizer summation circuit
| العنوان: | Decision feedback equalizer summation circuit |
|---|---|
| Patent Number: | 9,722,818 |
| تاريخ النشر: | August 01, 2017 |
| Appl. No: | 14/492237 |
| Application Filed: | September 22, 2014 |
| مستخلص: | A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. |
| Inventors: | Huang, Ming-Chieh (San Jose, CA, US); Chern, Chan-Hong (Palo Alto, CA, US); Chung, Tao Wen (San Jose, CA, US); Swei, Yuwen (Fremont, CA, US); Lin, Chih-Chang (San Jose, CA, US); Huang, Tsung-Ching (San Jose, CA, US) |
| Assignees: | Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW) |
| Claim: | 1. A summation circuit, comprising: a first current source including at least one first input for receiving a signal based on an input data signal and at least one second input for receiving at least a first feedback signal with a first weighting value; and a second current source having at least one third input for receiving the signal based on the input data signal, at least one fourth input for receiving an offset calibration signal that is provided by an RC circuit coupled to an output of the summation circuit, and at least one fifth input for receiving at least a second feedback signal with a second weighting value, wherein the RC circuit includes a resistor and a capacitor each directly coupled to the fourth input, wherein the summation circuit is configured to output at least one output signal based on the input data signal and the first and second feedback signals, and wherein the second weighting value is an updated version of the first weighting value until the at least one output signal converges to a pre-defined signal level. |
| Claim: | 2. The summation circuit of claim 1 , wherein the input data signal is a differential signal including first and second complementary signals. |
| Claim: | 3. The summation circuit of claim 1 , wherein the offset calibration signal is a DC offset signal. |
| Claim: | 4. The summation circuit of claim 2 , further comprising: a first transistor having a gate configured to receive the first complementary signal, a source coupled to a first node, and a drain coupled to the at least one first input of the first current source at a second node; and a second transistor having a gate configured to receive the second complementary signal, a source coupled to the first node, and a drain coupled to the at least third first input of the first current source at a third node. |
| Claim: | 5. The summation circuit of claim 4 , further comprising: a first resistor coupled to the drain of the first transistor and to the at least one first input of the first current source at the second node; and a second resistor coupled to the drain of the second transistor and to the at least one third input of the second current source at the third node. |
| Claim: | 6. The summation circuit of claim 4 , further comprising a third transistor having a drain coupled to the first node, a source coupled to a first power supply, and a gate configured to receive a reference voltage. |
| Claim: | 7. A circuit, comprising: a first transistor having a gate configured to receive a first signal of a differential input signal pair, a source coupled to a first node, and a drain coupled to a first output node; a second transistor having a gate configured to receive a second signal of a differential input signal pair, a source coupled to the first node, and a drain coupled to a second output node; a first current source circuit including: a first input coupled to the first output node, a second input coupled to the second output node, and a third input configured to receive at least a first feedback signal with a first weighting value; and a second current source circuit including: a first input coupled to the first output node, a second input coupled to the second output node, a third input configured to receive an offset calibration signal that is provided by a first RC circuit coupled to the first output node, wherein the RC circuit includes a resistor and a capacitor each directly coupled to the third input, and at least one fourth input for receiving at least a second feedback signal with a second weighting value, wherein the circuit is configured to output at least one output signal based on the differential input signal pair and the first and second feedback signals, and wherein the second weighting value is an updated version of the first weighting value until the at least one output signal converges to a pre-defined signal level. |
| Claim: | 8. The circuit of claim 7 , further comprising a first resistor coupled to the drain of the first transistor and to the at least one first input of the first current source at the first output node; and a second resistor coupled to the drain of the second transistor and to the at least one third input of the second current source at the second output node. |
| Claim: | 9. The circuit of claim 7 , further comprising a third transistor having a drain coupled to the first node, a source coupled to a first power supply, and a gate configured to receive a reference voltage. |
| Claim: | 10. The circuit of claim 7 , wherein the offset calibration signal is a DC offset signal. |
| Claim: | 11. The circuit of claim 7 , wherein the first and second output nodes are coupled respectively to a first input node of a flip-flop and to a second input node of the flip-flop. |
| Claim: | 12. The circuit of claim 11 , further comprising: a second RC circuit coupled to the second output node. |
| Claim: | 13. The circuit of claim 11 , wherein the at least one feedback signal is received from an internal node of the flip-flop. |
| Claim: | 14. The circuit of claim 11 , further comprising: a first RC circuit coupled to a first internal node of the flip-flop; and a second RC circuit coupled to a second internal node of the flip-flop. |
| Claim: | 15. The circuit of claim 12 , wherein the first RC circuit includes: a first resistor coupled between the first output node and a second node, and a first capacitor coupled to the second node and to the first voltage supply. |
| Claim: | 16. The circuit of claim 14 , wherein the first RC circuit includes a first resistor coupled to the first internal node of the flip-flop and to a second node that is coupled to the first current source; and a first capacitor coupled between the second node and the first power supply. |
| Claim: | 17. The circuit of claim 15 , wherein the second RC circuit includes: a second resistor coupled between the second output node and a third node, and a second capacitor coupled to the third node and to the first voltage supply. |
| Claim: | 18. The circuit of claim 16 , wherein the second RC circuit includes a second resistor coupled to the second internal node of the flip-flop and to a third node that is coupled to the first current source; and a second capacitor coupled between the third node and the first power supply. |
| Patent References Cited: | 4019118 April 1977 Harwood 5774003 June 1998 Qureshi et al. 6684074 January 2004 Hong et al. 7106099 September 2006 Nix 7358782 April 2008 Khanoyan et al. 7403760 July 2008 Gao 8537886 September 2013 Su 8637886 January 2014 Tsuji 2004/0239373 December 2004 Seshita 2005/0110550 May 2005 Shi 2008/0112507 May 2008 Smith et al. 2008/0159380 July 2008 Kris 2008/0187036 August 2008 Park et al. 2012/0128055 May 2012 Jiang 2161523 February 1977 |
| Other References: | Bulzcchelli, J.F., et al., “A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology”, IEEE Journal of Solid-State Circuits, Dec. 2006, 41(12):2885-2900. cited by applicant Ren, J, et al., “Performance Analysis of Edge-based DFE”, 2006 IEEE Electrical Performance of Electronic Packaging, pp. 265-268. cited by applicant Shoval, A., et al., “Comparison of DC Offset Effects in Four LMS Adaptive Algorithms”, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, Mar. 1995, 42(3):176-185. cited by applicant |
| Primary Examiner: | Cadeau, Wednel |
| Attorney, Agent or Firm: | Duane Morris LLP |
| رقم الانضمام: | edspgr.09722818 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |