Patent
Fly-over conductor segments in integrated circuits with successive load devices along a signal path
| العنوان: | Fly-over conductor segments in integrated circuits with successive load devices along a signal path |
|---|---|
| Patent Number: | 9,025,356 |
| تاريخ النشر: | May 05, 2015 |
| Appl. No: | 13/221081 |
| Application Filed: | August 30, 2011 |
| مستخلص: | The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset. |
| Inventors: | Lu, Hsiao-Wen (Guishan Township, Taoyuan County, TW); Hsieh, Wei-Jer (Hsinchu, TW); Cheng, Chiting (Taichung, TW); Chou, Chung-Cheng (Hsin-Chu, TW); Chang, Jonathan Tsung-Yung (Hsinchu, TW) |
| Assignees: | Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW) |
| Claim: | 1. An apparatus, comprising: a word line decoder having at least one output; and word line gating circuitry coupled to the at least one output of the word line decoder, the word line gating circuitry including a first set of logic gates, and a second set of logic gates positioned farther away from the output of the word line decoder than the first set of logic gates, wherein a fly-over conductor bypasses the first set of logic gates and couples the second set of logic gates to the first set of logic gates and to the at least one output of the word line decoder at a first common point located between the output of the word line decoder and the first set of logic gates. |
| Claim: | 2. The apparatus of claim 1 , wherein the first set of logic gates and the second set of logic gates are aligned in a single column. |
| Claim: | 3. The apparatus of claim 1 , wherein each of the logic gates of the first set and the second set has a respective output that is coupled to a respective word line. |
| Claim: | 4. The apparatus of claim 3 , wherein each word line is coupled to a respective plurality of bit cells. |
| Claim: | 5. The apparatus of claim 4 , wherein a plurality of bit cells coupled to a first word line is divided into a first set of bit cells and a second set of bits, the first set of bit cells being positioned closer to the output of a first logic gate that is coupled to the first word line than the second set of bit cells. |
| Claim: | 6. The apparatus of claim 5 , wherein each of the bit cells in the second set of bit cells is coupled to the second set of bit cells and to the first logic gate at a second common point located between an output of the first logic gate and the second set of bit cells. |
| Claim: | 7. The apparatus of claim 6 , wherein a second fly-over conductor bypasses the first set of bit cells and couples the first set of bit cells to the second set of bit cells and to the output of the first logic gate at the second common point. |
| Claim: | 8. The apparatus of claim 1 , further comprising a first inverter having an input coupled to the common point and an output coupled to each of the logic gates in the first set of logic gates; and a second inverter having an input coupled to the common point and an output coupled to each of the logic gates in the second set of logic gates. |
| Claim: | 9. A semiconductor memory comprising: a plurality of word lines each coupled to a respective plurality of bit cells; a word line decoder having at least one output; and word line gating circuitry coupled to the at least one output of the word line decoder, the word line gating circuitry including a first set of logic gates, and a second set of logic gates positioned farther away from the output of the word line decoder than the first set of logic gates, wherein a respective output of each of the logic gates in the first set of logic gates and the second set of logic gates is coupled to a respect one of the plurality of word lines, and wherein a fly-over conductor bypasses the first set of logic gates and couples the second set of logic gates to the first set of logic gates and to the at least one output of the word line decoder at a first common point located between the output of the word line decoder and the first set of logic gates. |
| Claim: | 10. The semiconductor memory of claim 9 , wherein the first set of logic gates and the second set of logic gates are aligned in a single column. |
| Claim: | 11. The semiconductor memory of claim 9 , wherein a plurality of bit cells coupled to a first word line is divided into a first set of bit cells and a second set of bits, the first set of bit cells being positioned closer to the output of a first logic gate that is coupled to the first word line than the second set of bit cells. |
| Claim: | 12. The semiconductor memory of claim 11 , wherein each of the bit cells in the second set of bit cells is coupled to the second set of bit cells and to the first logic gate at a second common point located between an output of the first logic gate and the second set of bit cells. |
| Claim: | 13. The semiconductor memory of claim 12 , wherein a second fly-over conductor bypasses the first set of bit cells and couples the first set of bit cells to the second set of bit cells and to the output of the first logic gate at the second common point. |
| Claim: | 14. The semiconductor memory of claim 9 , further comprising a first inverter having an input coupled to the first common point and an output coupled to each of the logic gates in the first set of logic gates; and a second inverter having an input coupled to the first common point and an output coupled to each of the logic gates in the second set of logic gates. |
| Claim: | 15. A semiconductor memory comprising: a word line decoder; a first set of logic gates coupled to an output of the word line decoder; and a second set of logic gates coupled to the output of the word line decoder; wherein a first fly-over conductor bypasses the first set of logic gates and couples the second set of logic gates to the first set of logic gates and to the at least one output of the word line decoder at a first common point located between the output of the word line decoder and the first set of logic gates, wherein at least one logic gate in either the first set of logic gates or the second set of logic gates is coupled to a first set of bit cells and to a second set of bit cells, wherein a second fly-over conductor bypasses the first set of bit cells and couples the second set of bit cells to an output of the at least one logic gate and to the first set of bit cells at a second common point located between the output of the at least one logic gate and the first set of bit cells. |
| Claim: | 16. The semiconductor memory of claim 15 , further comprising a first inverter having an input coupled to the first common point and an output coupled to each of the logic gates in the first set of logic gates; and a second inverter having an input coupled to the first common point and an output coupled to each of the logic gates in the second set of logic gates. |
| Claim: | 17. The semiconductor memory of claim 16 , further comprising: a third inverter having an input coupled to the output of the at least one logic gate and an output coupled to each of the bit cells in the first set of bit cells; and a fourth inverter having an input coupled to the second common point and an output coupled to each of the bit cells in the second set of bit cells. |
| Claim: | 18. The semiconductor memory of claim 15 , further comprising: a first inverter having an input coupled to the output of the at least one logic gate and an output coupled to each of the bit cells in the first set of bit cells; and a second inverter having an input coupled to the second common point and an output coupled to each of the bit cells in the second set of bit cells. |
| Current U.S. Class: | 365/63 |
| Patent References Cited: | 4958326 September 1990 Sakurai 5881006 March 1999 Yabe et al. 7570504 August 2009 Vo 7606057 October 2009 Wang et al. 2007/0201262 August 2007 Joshi et al. 04238191 August 1992 |
| Assistant Examiner: | Alrobaie, Khamdan |
| Primary Examiner: | Nguyen, Vanthu |
| Attorney, Agent or Firm: | Duane Morris LLP |
| رقم الانضمام: | edspgr.09025356 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |