Patent
Asynchronous clock dividers to reduce on-chip variations of clock timing
| العنوان: | Asynchronous clock dividers to reduce on-chip variations of clock timing |
|---|---|
| Patent Number: | 8,970,267 |
| تاريخ النشر: | March 03, 2015 |
| Appl. No: | 12/874627 |
| Application Filed: | September 02, 2010 |
| مستخلص: | This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence. |
| Inventors: | Damodaran, Raguram (Plano, TX, US); Chachad, Abhijeet Ashok (Plano, TX, US); Venkatasubramanian, Ramakrishnan (Plano, TX, US) |
| Assignees: | Texas Instruments Incorporated (Dallas, TX, US) |
| Claim: | 1. An integrated circuit comprising: a system clock circuit generating a system clock signal; a plurality of circuit modules disposed on the integrated circuit; and a plurality of module clock circuits, each clock generator circuit connected to said system clock circuit for receiving said system clock signal, connected to a corresponding one of said plurality of circuit modules and supplying a programmable clock signal to said corresponding circuit module, disposed proximate to said corresponding circuit module and distant from said system clock circuit; said at least one of said plurality of module clock circuits includes a programmable divider dividing said system clock signal by a programmable integral amount; and said at least one of said plurality of modules clock circuits includes: a plurality of finite state machines, each finite state machine having an input connected to said system clock circuit receiving said system clock signal and an output generating a clock gating signal for a predetermined division of said system clock, a clock gating signal multiplexer having a plurality of inputs, each input connected to a corresponding one of said plurality of finite state machines receiving a corresponding clock gating signal, an output and a control input receiving a clock selection signal, said multiplexer connecting one of said plurality of inputs to said output corresponding to said clock selection signal, and a clock gate having an input connected to said system clock circuit receiving said system clock, a gating input connected to said output of said multiplexer and an output supplying said programmable clock signal to said corresponding circuit module. |
| Claim: | 2. The integrated circuit of claim 1 , wherein: each of said finite state machines includes a multi-bit register having a multi-bit input, a clock input receiving said system clock signal and an multi-bit output; an incrementer having a multi-bit input connected to said multi-bit output of said multi-bit register and a multi-bit output, said incrementer generating said multi-bit output one greater than said multi-bit input; a source of a multi-bit reset signal, a multiplexer having a first input connected to said multi-bit output of said incrementer, a second input connected to said source of a multi-bit reset signal, an output connected to said multi-bit input of said multi-bit register and a control input receiving a control signal, said multiplexer connecting one of said first and second inputs to said output corresponding to said control signal. |
| Claim: | 3. The integrated circuit of claim 1 , further comprising: at least one integrated circuit input receiving a corresponding external clock signal; at least one of said plurality of modules clock circuits includes: a first gating circuit multiplexer having a first input connected to said system clock circuit receiving said system clock signal, at least one second input connected to a corresponding integrated circuit input receiving said corresponding external clock signal, an output connected to said input of said clock gate and a control input receiving a clock selection signal, said first gating multiplexer connecting one of said first and second inputs to said output corresponding to said clock selection signal, and a second gating circuit multiplexer having a first input connected to said output of said clock gating signal multiplexer, at least one second input connected to a corresponding integrated circuit input receiving said corresponding external clock signal, an output connected to said gating input of said clock gate and a control input receiving said clock selection signal, said second gating multiplexer connecting one of said first and second inputs to said output corresponding to said clock selection signal. |
| Claim: | 4. The integrated circuit of claim 3 , wherein: said at least one integrated circuit input receives a design for test clock signal. |
| Current U.S. Class: | 327/115 |
| Patent References Cited: | 5532633 July 1996 Kawai 2006/0091928 May 2006 Kapur |
| Primary Examiner: | Poos, John |
| Attorney, Agent or Firm: | Marshall, Jr., Robert D. Telecky, Jr., Frederick J. |
| رقم الانضمام: | edspgr.08970267 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |