Patent
Method and apparatus for read assist to compensate for weak bit
| العنوان: | Method and apparatus for read assist to compensate for weak bit |
|---|---|
| Patent Number: | 8,958,232 |
| تاريخ النشر: | February 17, 2015 |
| Appl. No: | 13/437081 |
| Application Filed: | April 02, 2012 |
| مستخلص: | A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. |
| Inventors: | Chang, Jonathan Tsung-Yung (Hsinchu, TW); Lee, Cheng Hung (Hsinchu, TW); Chou, Chung-Cheng (Hsin-Chu, TW); Liao, Hung-Jen (Hsin-Chu, TW); Lo, Bin-Hau (Hsinchu, TW) |
| Assignees: | Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW) |
| Claim: | 1. A memory assist apparatus comprising: a detection circuit configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold; and a compensation circuit configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. |
| Claim: | 2. The memory assist apparatus of claim 1 , wherein the detection circuit includes a PMOS transistor and a first NMOS transistor, a gate of the PMOS transistor and a gate of the first NMOS transistor are coupled to the bit line, and a drain terminal of the PMOS transistor is coupled to an input node of the compensation circuit. |
| Claim: | 3. The memory assist apparatus of claim 2 , wherein the detection circuit further includes a second NMOS transistor coupled between the PMOS transistor and the first NMOS transistor. |
| Claim: | 4. The memory assist apparatus of claim 3 , further comprising a sense amplifier coupled to the bit line, wherein the sense amplifier is enabled by assertion of a sense enable signal, and the second NMOS transistor is biased by a signal complementary to the sense enable signal. |
| Claim: | 5. The memory assist apparatus of claim 2 , wherein the bit cell is powered by a power supply voltage, and a source terminal of the PMOS transistor is coupled to a node having a voltage greater than or equal to the power supply voltage. |
| Claim: | 6. The memory assist apparatus of claim 2 , wherein the bit cell is powered by a power supply voltage, and a body of the PMOS transistor is coupled to a node having a voltage less than or equal to the power supply voltage. |
| Claim: | 7. The memory assist apparatus of claim 1 , wherein the compensation circuit includes a first NMOS transistor having a gate biased by the detection signal. |
| Claim: | 8. The memory assist apparatus of claim 7 , wherein the compensation circuit further includes a second NMOS transistor in a cascade configuration with the first NMOS transistor. |
| Claim: | 9. The memory assist apparatus of claim 8 , further comprising a sense amplifier coupled to the bit line, wherein the sense amplifier is enabled by assertion of a sense enable signal, and the second NMOS transistor is biased by the sense enable signal. |
| Claim: | 10. The memory assist apparatus of claim 1 , wherein the bit cell is a read only memory (ROM) bit cell. |
| Claim: | 11. The memory assist apparatus of claim 1 , wherein the bit cell is a static random access memory (SRAM) bit cell. |
| Claim: | 12. The memory assist apparatus of claim 11 , wherein the bit cell is selected from the group consisting of a 6T SRAM bit cell, an 8T SRAM bit cell, and a 10T SRAM bit cell. |
| Claim: | 13. A method of assisting a memory read operation, the method comprising the steps of: detecting, during a memory read operation, whether a bit line coupled to a memory bit cell has a voltage below a predetermined threshold, to provide a detection signal; and pulling down the voltage of the bit line, if the detection signal indicates that the voltage of the bit line is below the predetermined threshold, during the memory read operation. |
| Claim: | 14. The method of claim 13 , further comprising the steps of: sensing a logic state at the bit line responsive to assertion of a sense enable signal; wherein the detecting step includes: selectively conducting current from a first node to a second node having a logical high voltage value, to provide the detection signal at the logical high voltage value at the first node; and selectively providing an electrical path from the first node to a ground node based on a signal complementary to the sense enable signal, to provide the detection signal at a logical low voltage value at the first node. |
| Claim: | 15. The method of claim 13 , wherein the detecting includes inverting a logic state corresponding to a voltage value of the bit line. |
| Claim: | 16. The method of claim 13 , further comprising the step of sensing a logic state at the bit line responsive to assertion of a sense enable signal, wherein the pulling down the bit line is further based on the sense enable signal. |
| Claim: | 17. A memory comprising: a memory bit cell; a bit line coupled to the bit cell, the bit line configured to provide read access to a data bit stored at the bit cell; and an assist module including: a PMOS transistor including a gate terminal coupled to the bit line, and a source terminal coupled to an assist module power supply node; a first NMOS transistor including a gate terminal coupled to the bit line; a second NMOS transistor coupled between the PMOS transistor and the first NMOS transistor; a third NMOS transistor including a gate terminal coupled to a drain terminal of the PMOS transistor, and a drain terminal coupled to the bit line; and a fourth NMOS transistor including a drain terminal coupled to a source terminal of the third NMOS transistor; and a sense amplifier coupled to the bit line, the sense amplifier enabled by assertion of a sense enable signal; wherein the fourth NMOS transistor is biased by the sense enable signal, and the second NMOS transistor is biased by a signal complementary to the sense enable signal. |
| Claim: | 18. The memory of claim 17 , wherein: the bit cell is powered by a power supply voltage; a voltage at the assist module power supply node is greater than the power supply voltage; and a body of the PMOS transistor is coupled to a voltage less than the power supply voltage. |
| Claim: | 19. The memory of claim 17 , wherein the bit cell is a read only memory (ROM) bit cell. |
| Claim: | 20. The memory of claim 17 , wherein the bit cell is a static random access memory (SRAM) bit cell. |
| Current U.S. Class: | 365/94 |
| Patent References Cited: | 5034923 July 1991 Kuo et al. 5091879 February 1992 Tran 5396457 March 1995 Vinal 5428574 June 1995 Kuo et al. 6574159 June 2003 Ohbayashi et al. 6975532 December 2005 Kosonocky et al. 7177177 February 2007 Chuang et al. 7755937 July 2010 Kitagawa 8164962 April 2012 Takeda 8547723 October 2013 Tanaka et al. 2013/0010544 January 2013 Lin et al. 2014/0016391 January 2014 Tanaka et al. 2014/0269091 September 2014 Zheng et al. |
| Other References: | Zhang, K.J. et al., “A research of Dual-Port Sram cell using 8T”, 2010 10th IEEE International Conference on Solid State and Integrated Circuit Technology, Nov. 2010, pp. 2040-2042. cited by applicant |
| Primary Examiner: | Nguyen, Tuan T |
| Attorney, Agent or Firm: | Duane Morris LLP |
| رقم الانضمام: | edspgr.08958232 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |