Patent
Semiconductor device and method for manufacturing the same
| العنوان: | Semiconductor device and method for manufacturing the same |
|---|---|
| Patent Number: | 8,716,717 |
| تاريخ النشر: | May 06, 2014 |
| Appl. No: | 13/816511 |
| Application Filed: | April 15, 2011 |
| مستخلص: | A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple. |
| Inventors: | Kawakami, Tsuyoshi (Tokyo, JP); Furukawa, Akihiko (Tokyo, JP); Miura, Naruhisa (Tokyo, JP); Kagawa, Yasuhiro (Tokyo, JP); Hamada, Kenji (Tokyo, JP); Nakaki, Yoshiyuki (Tokyo, JP) |
| Assignees: | Mitsubishi Electric Corporation (Tokyo, JP) |
| Claim: | 1. A semiconductor device comprising: an active region formed in a surface of a semiconductor layer having a first conductive type; and a plurality of electric field relief layers that are defined by impurity regions having a second conductive type, said plurality of electric field relief layers being arranged from a peripheral portion of said active region toward the outside so as to surround said active region, wherein said plurality of electric field relief layers are configured such that an impurity implantation amount decreases from said active region side toward the outside, said plurality of electric field relief layers include: a first electric field relief layer whose entire region is implanted with an impurity having the second conductive type at a first surface density; a second electric field relief layer whose entire region is implanted with an impurity having the second conductive type at a second surface density; and a third electric field relief layer configured with a plurality of first small regions and a plurality of second small regions being alternately arranged, said first small region having a width in a plane direction smaller than that of said first electric field relief layer, said first small region being implanted with an impurity having the second conductive type at said first surface density, said second small region having a width in the plane direction smaller than that of said second electric field relief layer, said second small region being implanted with an impurity having the second conductive type at said second surface density, said third electric field relief layer is arranged between said first electric field relief layer and said second electric field relief layer with respect to the plane direction, and the average surface density of said third electric field relief layer takes a value between said first surface density and said second surface density. |
| Claim: | 2. The semiconductor device according to claim 1 , wherein in said plurality of electric field relief layers, a final electric field relief layer provided in the last when said active region is defined as the head is configured with a plurality of third small regions and a plurality of non-implanted regions being alternately arranged, said third small region having a width in the plane direction smaller than that of a pre-final electric field relief layer that immediately precedes said final electric field relief layer, said third small region being implanted with an impurity having the second conductive type at a surface density equal to that of said pre-final electric field relief layer, said non-implanted region being formed of said semiconductor layer not implanted with an impurity having the second conductive type. |
| Claim: | 3. The semiconductor device according to claim 1 , wherein in said second electric field relief layer, the depth of implantation in the impurity region thereof is greater than the depth of implantation in the impurity region of said first electric field relief layer. |
| Claim: | 4. The semiconductor device according to claim 3 , wherein an impurity region that is formed simultaneously with said impurity region of said second electric field relief layer so as to have a depth and an impurity concentration equal to those of said impurity region of said second electric field relief layer contains, with respect to a cross-sectional direction, an impurity region that is formed simultaneously with said impurity region of said first electric field relief layer so as to have a depth and an impurity concentration equal to those of said impurity region of said first electric field relief layer. |
| Claim: | 5. The semiconductor device according to claim 1 , wherein in a case where said first electric field relief layer is provided adjacent to said active region, the depth of implantation and an implanted region of said impurity region are set such that said impurity region of said first electric field relief layer covers the peripheral portion of said active region or the whole of said active region. |
| Claim: | 6. The semiconductor device according to claim 5 , wherein said first electric field relief layer also serves as said active region. |
| Claim: | 7. The semiconductor device according to claim 1 , wherein said third electric field relief layer is formed such that one of said first and second small regions having a larger implantation amount have a constant width with respect to the plane direction, while the other of said first and second small regions having a smaller implantation amount have their width with respect to the plane direction gradually increasing at a location farther from said active region. |
| Claim: | 8. The semiconductor device according to claim 1 , wherein said third electric field relief layer formed such that one of said first and second small regions having a larger implantation amount have their width with respect to the plane direction gradually decreasing at a location farther from said active region, while the other of said first and second small regions having a smaller implantation amount have their width with respect to the plane direction gradually increasing at a location farther from said active region. |
| Claim: | 9. The semiconductor device according to claim 1 , wherein said active region corresponds to an anode region of a PN junction diode. |
| Claim: | 10. The semiconductor device according to claim 1 , wherein said active region corresponds to a region located below a Schottky electrode of a Schottky barrier diode. |
| Claim: | 11. The semiconductor device according to claim 1 , wherein said active region corresponds to a partial region of a transistor including a MOSFET, an IGBT, a BJT. |
| Claim: | 12. The semiconductor device according to claim 11 , wherein said active region corresponds to a drain region of an LDMOSFET (Laterally Diffused MOSFET) having a source electrode, a gate electrode, and a drain electrode arranged in the plane direction on a main surface of said semiconductor layer, said plurality of electric field relief layers are arranged between said drain region and a well region including a source region. |
| Claim: | 13. The semiconductor device according to claim 1 , wherein said semiconductor layer is made of a wide band-gap semiconductor. |
| Claim: | 14. A method for manufacturing the semiconductor device according to claim 1 , said method comprising the steps of: (a) forming a first implantation mask on said semiconductor layer and ion-implanting the impurity having the second conductive type at said first surface density, to thereby form said first electric field relief layer and said first small regions; and (b) after said step (a), forming a second implantation mask on said semiconductor layer and ion-implanting the impurity having the second conductive type at said second surface density, to thereby form said second electric field relief layer and said second small regions. |
| Claim: | 15. A method for manufacturing the semiconductor device according to claim 1 , said method comprising the steps of: (a) forming a first implantation mask on said semiconductor layer and ion-implanting the impurity having the second conductive type at said second surface density, so that an impurity layer that is identical to said second electric field relief layer is formed in a region where said first electric field relief layer is formed, and said second small regions are also formed; and (b) after said step (a), forming, on said semiconductor layer, a second implantation mask that covers at least said second electric field relief layer, and ion-implanting the impurity having the second conductive type at a surface density that, when added to said second surface density, results in said first surface density, to thereby form said first electric field relief layer and said first small regions. |
| Current U.S. Class: | 257/76 |
| Patent References Cited: | 6002159 December 1999 Bakowski et al. 6040237 March 2000 Bakowski et al. 6831345 December 2004 Kinoshita et al. 7049675 May 2006 Kinoshita et al. 7919403 April 2011 Tarui 8106451 January 2012 Khalil 8350353 January 2013 Tarui 2008/0224150 September 2008 Suzuki et al. 2009/0212301 August 2009 Zhang et al. 2010/0148823 June 2010 Shimizu 2011/0180870 July 2011 Pendharkar 2000 516767 December 2000 3708057 October 2005 3997551 October 2007 2008 103529 May 2008 2010 267783 November 2010 2009 108268 September 2009 |
| Other References: | Stengl, R., et al., “Variation of Lateral Doping-A New Concept to Avoid High Voltage Breakdown of Planar Junctions,” IEDM, vol. 85, No. 6.4, pp. 154-157 (1985). cited by applicant International Search Report Issued Jul. 19, 2011 in PCT/JP11/59397 Filed Apr. 15, 2011. cited by applicant English Translation of the International Preliminary Report on Patentability issued May 2, 2013 in PCT/JP2011/059397. cited by applicant English Translation of the Written Opinion of the International Searching Authority issued Jul. 19, 2011 in PCT/JP2011/059397. cited by applicant |
| Primary Examiner: | Diallo, Mamadou |
| Attorney, Agent or Firm: | Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
| رقم الانضمام: | edspgr.08716717 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |