Patent
Process variability tolerant programmable memory controller for a pipelined memory system
| العنوان: | Process variability tolerant programmable memory controller for a pipelined memory system |
|---|---|
| Patent Number: | 8,488,405 |
| تاريخ النشر: | July 16, 2013 |
| Appl. No: | 13/184873 |
| Application Filed: | July 18, 2011 |
| مستخلص: | In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency. |
| Inventors: | Chachad, Abhijeet Ashok (Plano, TX, US); Venkatasubramanian, Ramakrishnan (Plano, TX, US); Damodaran, Raguram (Plano, TX, US) |
| Assignees: | Texas Instruments Incorporated (Dallas, TX, US) |
| Claim: | 1. An integrated circuit comprising: a pipelined memory array, the pipelined memory array comprising a plurality of memory banks; a memory control circuit configured to select the number of clock cycles used for a read latency in the pipelined memory array partially based on the read access time information of a memory bank, wherein the read access time information of the memory bank is provided to the memory control circuit through one or more efuse registers. |
| Claim: | 2. The integrated circuit of claim 1 wherein the read access time information of the memory bank is provided to the memory control circuit through one or more pins on the integrated circuit. |
| Claim: | 3. The integrated circuit of claim 1 wherein access latency is determined by the number of pipelined memory banks in the plurality of memory banks. |
| Claim: | 4. The integrated circuit of claim 1 wherein the memory control circuit controls how much time expires between consecutive accesses of a particular memory bank in the plurality of memory banks. |
| Claim: | 5. The integrated circuit of claim 4 wherein the time that expires between consecutive accesses of the particular memory bank in the plurality of memory banks is equal to or greater than an access latency. |
| Claim: | 6. The integrated circuit of claim 1 wherein data may be read from the pipelined memory array every clock cycle when the read access addresses are consecutive. |
| Claim: | 7. The integrated circuit of claim 1 wherein the memory control circuit comprises: a plurality of delay circuits connected in series wherein each delay circuit in the plurality of delay circuits has an input and an output; a multiplexer having data inputs, select inputs and an output; the data inputs of the multiplexer each connected to an output of a delay circuit; a control logic circuit connected to the select inputs of the multiplexer wherein the control logic circuit selects which input of the multiplexer is transferred to the output of the multiplexer; wherein the output of the multiplexer together with a clock determines when data from the pipelined memory array is captured in registers. |
| Claim: | 8. The integrated circuit of claim 7 wherein the memory control circuit further comprises: memory enable outputs that select which memory bank in the plurality of memory banks may be accessed. |
| Current U.S. Class: | 3652/257 |
| Patent References Cited: | 6134178 October 2000 Yamazaki et al. 6154417 November 2000 Kim 6745309 June 2004 Jeddeloh et al. 7800974 September 2010 Zhang et al. |
| Primary Examiner: | Byrne, Harry W |
| Attorney, Agent or Firm: | Pessetto, John R. Brady, W. James Telecky, Jr., Frederick J. |
| رقم الانضمام: | edspgr.08488405 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |