Patent
Tank tuning for band pass filter used in radio communications
| العنوان: | Tank tuning for band pass filter used in radio communications |
|---|---|
| Patent Number: | 8,130,053 |
| تاريخ النشر: | March 06, 2012 |
| Appl. No: | 12/417446 |
| Application Filed: | April 02, 2009 |
| مستخلص: | A tuning method and circuit for an LC tank resonant circuit, including an inductor and a variable capacitor, are described. In a tuning mode, an RF input signal is applied to an input port of the circuit, and the RF output signal is monitored as a variable capacitor control input is varied. A peak output is detected, and the corresponding variable capacitor control input is stored, and applied to the variable capacitor in an operating mode. In one embodiment, the variable capacitor control input is adjusted for delay in the peak detection process. In one embodiment, the variable capacitor comprises a coarse capacitor and a fine capacitor; the tuning procedure is repeated for each capacitor; and both coarse and fine variable capacitor control inputs are stored and applied to the respective capacitors in operating mode. |
| Inventors: | Mu, Fenghao (Hjärup, SE) |
| Assignees: | Telefonaktiebolaget LM Ericsson (publ) (Stockholm, SE) |
| Claim: | 1. A method of tuning a LC tank circuit, and outputting a radio frequency (RF) signal responding to an input RF signal, the LC tank circuit comprising an inductor and a variable capacitor having independently variable coarse and fine capacitances wherein the coarse capacitance is greater than the fine capacitance, the method comprising: in a coarse phase of a tuning mode, incrementing/decrementing a control input to the coarse variable capacitor to vary its capacitance between a minimum and maximum value; monitoring the magnitude of the output RF signal as the control input changes; detecting a peak in the output RF signal; and storing the coarse variable capacitor control input value associated with the output RF signal peak; in a fine phase of a tuning mode, applying the stored coarse variable capacitor control input value to the variable capacitor; incrementing/decrementing a control input to the fine variable capacitor to vary its capacitance between a minimum and maximum value; monitoring the magnitude of the output RF signal as the control input changes; detecting a peak in the output RF signal; and storing the fine variable capacitor control input value associated with the output RF signal peak; and in an operating mode, applying the stored coarse and fine variable capacitor control input values to the respective coarse and fine capacitances of the variable capacitor. |
| Claim: | 2. The method of claim 1 wherein incrementing the control input comprises advancing a digital counter. |
| Claim: | 3. The method of claim 1 wherein storing the respective coarse or fine variable capacitor control input value associated with an output RF signal peak comprises storing the respective prior variable capacitor control input value, to account for delay in detecting a peak in the output RF signal. |
| Claim: | 4. The method of claim 1 wherein detecting a peak in the output RF signal comprises detecting a change in the algebraic sign of the slope of the output RF signal magnitude as a function of the respective coarse or fine variable capacitor control input value. |
| Claim: | 5. The method of claim 4 wherein detecting a change in the algebraic sign of the slope of the output RF signal magnitude as a function of the respective variable capacitor control input value comprises applying a first respective variable capacitor control input value; sampling and holding the output RF signal magnitude with the first respective variable capacitor control input value applied; applying a second respective variable capacitor control input value; sampling and holding the output RF signal magnitude with the second respective variable capacitor control input value applied; comparing the sampled output RF signal magnitudes in a comparator; and detecting a change in the polarity of the comparator output. |
| Claim: | 6. The method of claim 5 further comprising applying positive feedback to the comparator to provide hysteresis to the inputs. |
| Claim: | 7. A radio frequency (RF) circuit, comprising: an input port operative to receive an input RF signal; an LC tank circuit comprising an inductor and a variable capacitor having independently variable coarse and fine capacitances wherein the coarse capacitance is greater than the fine capacitance and receiving respective coarse and fine control inputs, and operative to output an RF signal responsive to the input RF signal; and a tuning circuit comprising a peak detector operative to detect a peak in the magnitude of the output RF signal; a controller operative, in respective coarse and fine tuning modes, to receive a peak detection indication and operative to output the respective coarse and fine control inputs to the variable capacitor; and a memory element operative to store the coarse and fine variable capacitor control inputs. |
| Claim: | 8. The circuit of claim 7 wherein the memory element comprises a first memory element operative to store the coarse capacitor control input and a second memory element operative to store the fine capacitor control input. |
| Claim: | 9. The circuit of claim 7 wherein the variable capacitor includes a varactor, and further comprising a digital to analog converter interposed between the memory element and the varactor. |
| Claim: | 10. The circuit of claim 7 wherein the controller, in each of coarse and fine tuning modes, is operative to: vary the value of a respective coarse or fine variable capacitor control input; receive an indication of a peak in the magnitude of the output RF signal; and output the value of the respective variable capacitor control input associated with the output RF signal peak. |
| Claim: | 11. The circuit of claim 10 wherein the memory elements are operative to store, and to output to the variable capacitor in an operating mode, the respective coarse and fine values of the variable capacitor control inputs associated with the respective output RF signal peaks. |
| Claim: | 12. The circuit of claim 10 wherein the controller, in the tuning mode, is further operative to output the prior value of each of the respective coarse and fine variable capacitor control inputs upon receiving the peak indication, to account for delay in detecting each peak. |
| Claim: | 13. The circuit of claim 10 wherein the peak detector comprises: an RF detector operative to detect the magnitude of the output RE signal; a first sample-and-hold circuit connected to the RF detector and operative to store a first value of the magnitude of the output RF signal; a second sample-and-hold circuit connected to the RF detector and operative to store a second value of the magnitude of the output RF signal; a comparator operative to compare the first value of the magnitude of the output RF signal associated with a first value of the respective coarse or fine variable capacitor control input, with the second value of the magnitude of the output RF signal associated with a second value of the respective coarse or fine variable capacitor control input, and further operative to output an indication which RF signal value is greater. |
| Claim: | 14. The circuit of claim 10 wherein the peak detector comprises: a first combined RF detector and sample-and-hold circuit operative to detect and store a first value of the magnitude of the output RF signal; a second combined RF detector and sample-and-hold circuit operative to detect and store a second value of the magnitude of the output RF signal; and a comparator operative to compare the stored RF signal magnitude values and to output an indication which RF signal value is greater. |
| Claim: | 15. The circuit of claim 14 , wherein the combined RF detector and sample-and-hold circuit comprises: a rectifier comprising two transistors; two transmission gates connect to inputs of the rectifier; a capacitor connect to an output of the rectifier and operative as sampling capacitor; and a bias circuit operative to set bias voltage to the rectifier to zero during a hold period and to a normal bias during a sampling period. |
| Claim: | 16. The circuit of claim 7 wherein the controller comprises: a counter; first and a second memory elements operative to store different output values of the counter; a third memory element operative to store an indication of detection of a peak in the magnitude of the output RF signal; and a multiplexer operative to output a value of the counter during a tuning mode and a calculated value during an operating mode. |
| Claim: | 17. The circuit of claim 16 wherein: the counter is operative to successively output increasing/decreasing values for the respective coarse or fine control input of the variable capacitor; the first memory element is operative to store the output of the counter upon receiving from the peak detector the indication of detection of a peak in the magnitude of the output RF signal; the second memory element is operative to store the output of the counter upon receiving the delayed indication of detection of a peak in the magnitude of the output RF signal; and a linear operating processor operative to receive the two values of counter outputs from the first and second memory elements, and further operative to calculate the calculated value corresponding to the counter output value prior to receipt of the peak detection indication. |
| Claim: | 18. The circuit of claim 17 wherein the linear operating processor implements the equation V no=(k+ 1) V n+1 −kV n+2 where V no is the counter output value prior to receipt of the peak detection indication; V n+1 is the output of the first memory element; V n+2 is the output of the second memory element; and k is a positive number, corresponding to the number of delays from the time where the output RF signal reaches its peak. |
| Claim: | 19. The circuit of claim 7 , further comprising a plurality of cascaded stages, each stage comprising: an LC tank circuit comprising a variable capacitor having independently variable coarse and fine capacitances and receiving respective coarse and fine control inputs and an inductor; and a memory element operative to store a variable capacitor control input. |
| Claim: | 20. The circuit of claim 19 , wherein each stage further comprises a peak detector. |
| Claim: | 21. The circuit of claim 20 , wherein each stage further comprises a controller. |
| Current U.S. Class: | 333/171 |
| Patent References Cited: | 6307442 October 2001 Meyer et al. 6307443 October 2001 Gabara 7016388 March 2006 Klene et al. 7102465 September 2006 Utsunomiyo et al. 7126403 October 2006 Kenney, Jr. et al. 7161416 January 2007 Gangi 7449970 November 2008 Yu et al. 7761067 July 2010 Tsai et al. 7855610 December 2010 Taghivand et al. 2004/0012450 January 2004 Nguyen 1630960 March 2006 00/70757 November 2000 03/038999 May 2003 |
| Other References: | Wiser, R., et al., “A 5-GHz wireless LAN transmitter with integrated tunable high-Q RF filter.” Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE. Sep. 21-24, 2008, San Jose, CA. pp. 607-610. IEEE, Piscataway, NJ. cited by other Liu, H., et al., “An automatic tuning scheme for high frequency bandpass filters.” Circuits and Systems, 2002, IEEE International Symposium on. ISCAS 2002. vol. 3, May 26-29, 2002, Scottsdale, AZ. pp. III-551-III-554. IEEE, Piscataway, NJ. cited by other Chang, Y., et al., “On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters.” ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems, 2001. vol. 4, May 6-9, 2001, Sydney, Australia. pp. 246-249. IEEE, Piscataway, NJ. cited by other Barnett, K., et al., “A multi-standard mobile digital video receiver in 0.18μm CMOS process.” 34th European Solid-State Circuits Conference, 2008. ESSCIRC 2008. Sep. 15-19, 2008, Edinburgh, Scotland. pp. 154-157. Institute of Physics (IOP), London, UK. cited by other Mirzaei, A., et al., “Low-Power WCDMA Transmitter with an Integrated Notch Filter.” IEE International Solid-State Circuits Conference. ISSCC 2008. Feb. 3-7, 2008, San Francisco, CA. pp. 212-213. IEEE, Piscataway, NJ. cited by other Pozsgay, A. et al., “A fully digital 65nm CMOS transmitter for the 2.4-to-2.7GHz WiFi/WiMax bands using 5.4GHz ΔΣRF DACs.” IEE International Solid-State Circuits Conference. ISSCC 2008. Feb. 3-7, 2008, San Francisco, CA. pp. 360-361. IEEE, Piscataway, NJ. cited by other |
| Primary Examiner: | Takaoka, Dean O |
| Attorney, Agent or Firm: | Coats & Bennett, P.L.L.C. |
| رقم الانضمام: | edspgr.08130053 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |