Patent
Mains phase detection apparatus
| العنوان: | Mains phase detection apparatus |
|---|---|
| Patent Number: | 7,646,225 |
| تاريخ النشر: | January 12, 2010 |
| Appl. No: | 12/093532 |
| Application Filed: | November 16, 2006 |
| مستخلص: | The present invention relates to an apparatus for accurately detecting a mains phase. The apparatus is constructed with a zero-crossing detector, a digital phase detector, a digital loop filter, and a digital controlled oscillator (DCO) of a direct digital synthesized (DDS) manner. The present apparatus employs an all-digital loop architecture and a high sampling clock to recover a signal with a phase orthogonal with the mains signal and a frequency the same as the mains signal. And jitters in the recovered signal are less than 10 us. The present apparatus is capable of implementing signal tracking of a zero frequency error and a zero phase in a wide range, and can provide a detection result of excellent performance for the power line carrier communication, mains frequency detection, etc. |
| Inventors: | Song, Chaosheng (Shanghai, CN); Gou, Gang (Shanghai, CN) |
| Assignees: | Miartech, Inc. (Shanghai, CN) |
| Claim: | 1. A mains phase detection apparatus comprises a zero-crossing detector, wherein said mains phase detection apparatus further comprises: an all-digital phase-locked loop, wherein said all-digital phase-locked loop comprises an edge detector, a digital phase detector, a digital loop filter, and a phase accumulator, wherein said edge detector couples said zero-crossing detector, and is triggered by either a rising edge or a falling edge of an output signal of said zero-crossing detector to generate a detecting pulse; and wherein said digital phase detector couples said zero-crossing detector and said phase accumulator to generate a phase difference signal between output signals of said zero-crossing detector and said phase accumulator; and wherein said digital loop filter couples said edge detector and said digital phase detector to perform low-pass filtering between each two detecting pulses of said edge detector; and wherein said phase accumulator is coupled to said digital loop filter, wherein a most significant bit of said phase accumulator is an output signal output to said digital phase detector. |
| Claim: | 2. The mains phase detection apparatus of claim 1 , wherein said digital phase detector comprises an exclusive-OR gate. |
| Claim: | 3. The mains phase detection apparatus of claim 1 , wherein said digital loop filter comprises an accumulator, a proportion regulator, an integrator, a first adder, and a second adder, wherein an input terminal of said accumulator is coupled to an output terminal of said digital phase detector, and input terminals of said proportion regulator and said integrator are coupled to an output terminal of said accumulator; and wherein two input terminals of said first adder are respectively coupled to output terminals of said proportion regulator and said integrator, and said second adder has two input terminals, wherein one input terminal is coupled to an output terminal of said first adder, and the other input terminal is set with an initial frequency word, wherein said accumulator is reset responsive to said detecting pulse, and accumulates an output signal of said phase detector between two of said detecting pulses. |
| Claim: | 4. The mains phase detection apparatus of claim 3 , wherein said initial frequency word corresponds to a frequency between 53˜57 Hz. |
| Claim: | 5. The mains phase detection apparatus of claim 3 , wherein said initial frequency word corresponds to a frequency of 55 Hz. |
| Current U.S. Class: | 327/156 |
| Patent References Cited: | 5485484 January 1996 Williams et al. 5539346 July 1996 Goto 5590157 December 1996 Schuur 6956924 October 2005 Linsky et al. 7394884 July 2008 Kaylani et al. 2003/0062955 April 2003 Lee et al. 1396710 February 2003 1422827 May 2004 |
| Assistant Examiner: | Nguyen, Hai L |
| Primary Examiner: | Donovan, Lincoln |
| Attorney, Agent or Firm: | Quarles & Brady LLP |
| رقم الانضمام: | edspgr.07646225 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |