Patent
Crack protection for silicon die
| العنوان: | Crack protection for silicon die |
|---|---|
| Patent Number: | 7,508,052 |
| تاريخ النشر: | March 24, 2009 |
| Appl. No: | 11/141859 |
| Application Filed: | June 01, 2005 |
| مستخلص: | A wafer containing a plurality of die separated by streets which are to be sawn has a nitride passivation layer which has openings over die contact locations and gaps leaving nitride strips along the streets. The gaps in the nitride along the streets expose an oxide, preferably TEOS. A nickel/gold plate contact material overlies the nitride layer and contacts the exposed die contact areas but does not adhere to either the nitride surface or the oxide surfaces. A saw blade can then cut along the streets without being gummed by the metalizing and without producing cracks which propagate into the die termination areas. |
| Inventors: | Burke, Hugo R. G. (Wales, GB); Arzumanyan, Aram (Burbank, CA, US) |
| Assignees: | International Rectifier Corporation (El Segundo, CA, US) |
| Claim: | 1. A wafer of semiconductor material having a plurality of identical laterally spaced die areas thereon which are surrounded by streets to be sawn to separate the die; said wafer having a surface passivation layer of nitride thereon; said surface passivation layer having openings therethrough at locations of electrodes on said die to permit the formation of contacts to said electrodes, said surface passivation layer having spaced parallel gaps on the borders of said streets separating said streets from said openings to leave a strip of nitride over each of said streets; each of said gaps having an oxide strip therein bordered on at least two sides by the surface passivation layer; whereby said streets can be sawn to singulate said die without propagation of cracks into a termination area of said die. |
| Claim: | 2. The wafer of claim 1 , wherein said semiconductor material is monocrystalline silicon. |
| Claim: | 3. The wafer of claim 2 , wherein said surface passivation layer is Si 3 N 4 . |
| Claim: | 4. The wafer of claim 3 , wherein said oxide strip is TEOS. |
| Claim: | 5. The wafer of claim 4 , wherein said electrodes are a nickel/gold plating. |
| Claim: | 6. The wafer of claim 1 , wherein said surface passivation layer is Si 3 N 4 . |
| Claim: | 7. The wafer of claim 1 , wherein said oxide strip is TEOS. |
| Claim: | 8. The wafer of claim 1 , wherein said electrodes receive a nickel/gold plating. |
| Claim: | 9. The wafer of claim 1 , wherein the surface passivation layer overlies at least a portion of the oxide strip. |
| Current U.S. Class: | 257/620 |
| Patent References Cited: | 5024970 June 1991 Mori 5844304 December 1998 Kata et al. 6365958 April 2002 Ibnabdeljalil et al. 2003/0100143 May 2003 Mulligan et al. 2005/0116333 June 2005 Akiyama |
| Assistant Examiner: | Roland, Christopher M |
| Primary Examiner: | Monbleau, Davienne |
| Attorney, Agent or Firm: | Ostrolenk, Faber, Gerb & Soffen, LLP |
| رقم الانضمام: | edspgr.07508052 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |