Patent
N-well and N + buried layer isolation by auto doping to reduce chip size
| العنوان: | N-well and N + buried layer isolation by auto doping to reduce chip size |
|---|---|
| Patent Number: | 7,436,043 |
| تاريخ النشر: | October 14, 2008 |
| Appl. No: | 11/019753 |
| Application Filed: | December 21, 2004 |
| مستخلص: | A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL. |
| Inventors: | Sung, Tzu-Chiang (Jhubei, TW); Huang, Chih Po (HsinChu, TW); Yeh, Rann Shyan (Hsin-Chu, TW); Liu, Jun Xiu (Hsinchu, TW); Chang, Chi-Hsuen (Hsinchu, TW); Chen, Chung-I (Hsinchu, TW) |
| Assignees: | Taiwan Semiconductor Manufacturing Co., Ltd (Hsin-Chu, TW) |
| Claim: | 1. A semiconductor device comprising a plurality of low voltage N-well (LVNW) areas, a plurality of low voltage P-well (LVPW) areas interposed between said LVNW areas and said LVNW and LVPW areas subjacently separated from a semiconductor substrate by a common N + buried layer (NBL), a common P + buried layer (PBL) formed directly beneath said plurality of LVNW areas and said plurality of LVPW areas and above said NBL such that each of said plurality of LVNW areas and each of said plurality of LVPW areas physically contacts said PBL, said plurality of LVNW areas and said plurality of LVPW areas laterally separated from said semiconductor substrate by a high voltage N-well (HVNW) area that surrounds said PBL. |
| Claim: | 2. The semiconductor device as in claim 1 , wherein said semiconductor substrate comprises a P-type silicon substrate. |
| Claim: | 3. The semiconductor device as in claim 2 , wherein said semiconductor substrate includes a negative voltage potential. |
| Claim: | 4. The semiconductor device as in claim 1 , wherein said PBL comprises indium as a dopant impurity therein. |
| Claim: | 5. The semiconductor device as in claim 1 , wherein said NBL is a first layer formed within said semiconductor substrate, said PBL is a second layer formed over said NBL and said LVNW areas and said LVPW areas are formed in a third layer formed over said PBL. |
| Claim: | 6. The semiconductor device as in claim 5 , wherein said third layer includes a surface contactable by at least one voltage source. |
| Claim: | 7. The semiconductor device as in claim 1 . wherein said NBL is disposed in a designated low voltage area of said semiconductor substrate. |
| Claim: | 8. The semiconductor device as in claim 1 , wherein said plurality of LVNW areas are biased at different potentials. |
| Claim: | 9. The semiconductor device as in claim 1 , wherein said NBL comprises Sb as a dopant impurity therein. |
| Claim: | 10. The semiconductor device as in claim 1 , wherein said plurality of low voltage N-well (LVNW) areas and said plurality of low voltage P-well (LVPW) areas are disposed in an epitaxial layer of P-type material disposed over said semiconductor substrate. |
| Claim: | 11. A semiconductor device comprising a plurality of low voltage N-well (LVNW) areas and a plurality of low voltage P-well (LVPW) areas disposed in an epitaxial layer of P-type material disposed over a semiconductor substrate, said LVPW areas interposed directly between said LVNW areas, said LVNW and LVPW areas subjacently separated from said semiconductor substrate by a common N + buried layer (NBL), a common P + buried layer (PBL) formed directly beneath said plurality of LVNW areas and said plurality of LVPW areas and above said NBL such that each of said plurality of LVNW areas and each of said plurality of LVPW areas physically contacts said PBL, said plurality of LVNW areas and said plurality of LVPW areas laterally separated from said semiconductor substrate by a high voltage N-well (HVNW) area that surrounds said PBL. |
| Current U.S. Class: | 257/500 |
| Patent References Cited: | 5156989 October 1992 Williams et al. 5786617 July 1998 Merrill et al. 6403992 June 2002 Wei 6594132 July 2003 Avery 2003/0122195 July 2003 Tada et al. 2005/0056907 March 2005 Maeda |
| Other References: | Wolf et al., Silicon Processing for the VLSI Era, 2000, Lattice Press, vol. 2 2nd ed., p. 832. cited by examiner |
| Assistant Examiner: | Lulis, Michael |
| Primary Examiner: | Elms, Richard T. |
| Attorney, Agent or Firm: | Duane Morris LLP |
| رقم الانضمام: | edspgr.07436043 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |