Patent
Phase controlled oscillator circuit with input signal coupler
| العنوان: | Phase controlled oscillator circuit with input signal coupler |
|---|---|
| Patent Number: | 7,414,489 |
| تاريخ النشر: | August 19, 2008 |
| Appl. No: | 11/440824 |
| Application Filed: | May 25, 2006 |
| مستخلص: | An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal. |
| Inventors: | Dally, William J. (Stanford, CA, US); Farjad-Rad, Ramin (Mountain View, CA, US); Poulton, John W. (Chapel Hill, NC, US); Greer, III, Thomas H. (Chapel Hill, NC, US); Ng, Hiok-Tiaq (Redwood City, CA, US); Stone, Teva J. (San Jose, CA, US) |
| Assignees: | Rambus Inc. (Los Altos, CA, US) |
| Claim: | 1. A clock multiplier, comprising: a pulse generator to generate a pulse stream in response to receiving a reference clock; and an oscillator circuit to generate an oscillating signal, the oscillator circuit having a frequency controlled by a control signal and receiving the pulse stream from the pulse generator, the pulse stream pulling the oscillator circuit into lock such that the oscillating signal is phase aligned with the pulse stream and has a frequency that is a multiple of a frequency of the reference clock. |
| Claim: | 2. The clock multiplier of claim 1 , wherein the multiple of the frequency of the reference clock is the closest multiple to the frequency of the oscillator circuit. |
| Claim: | 3. The clock multiplier of claim 1 , wherein the oscillator circuit includes one of an inverter ring oscillator, an LC oscillator, and a source-coupled ring oscillator. |
| Claim: | 4. The clock multiplier of claim 1 , wherein each pulse in the pulse stream adjusts the phase of the oscillating signal with a magnitude of correction smaller than and proportional to a difference in phase between the pulse stream and the oscillating signal. |
| Claim: | 5. The clock multiplier of claim 1 , wherein each pulse in the pulse stream is about a half period of the oscillating signal. |
| Claim: | 6. The clock multiplier of claim 1 , wherein the oscillator circuit includes a coupler and a free-running oscillator, the coupler coupling the pulse stream into the free-running oscillator to cause phase adjustments in the oscillating signal, the phase adjustments acting to pull the frequency of the oscillating signal to the multiple of the frequency of the reference clock. |
| Claim: | 7. The clock multiplier of claim 6 , wherein the free-running oscillator is selected from a group consisting of an inverter ring oscillator, an LC oscillator, and a source-coupled ring oscillator. |
| Claim: | 8. The clock multiplier of claim 6 , wherein the coupling is gated so that it is active only during each pulse in the pulse stream. |
| Claim: | 9. The clock multiplier of claim 8 , wherein the coupler includes a pair of field-effect transistors. |
| Claim: | 10. The clock multiplier of claim 9 , wherein each pulse in the pulse stream adjusts the phase of the oscillating signal with a magnitude of correction proportional to a size of the pair of field-effect transistors. |
| Claim: | 11. The clock multiplier of claim 1 , wherein the oscillator circuit includes first and second oscillators each having a frequency controlled by the control signal, the first oscillator outputting the oscillating signal, the second oscillator being a replica of the first oscillator and a part of a loop circuit that adjusts the control signal so that the frequency of the second oscillator is N times the frequency of the reference clock. |
| Claim: | 12. A clock multiplier, comprising: a delay circuit to receive a reference clock and to generate a delayed reference clock; and an oscillator circuit to generate an oscillating signal, the oscillator circuit having a frequency controlled by a control signal and including a coupler to receive both the reference clock and the delayed reference clock and to pull the oscillator circuit into lock such that the oscillating signal is phase aligned with the reference clock and has a frequency that is a multiple of a frequency of the reference clock. |
| Claim: | 13. The clock multiplier of claim 12 , wherein the multiple of the frequency of the reference clock is the closest multiple to the frequency of the oscillator circuit. |
| Claim: | 14. The clock multiplier of claim 12 , wherein the oscillator circuit includes one of an inverter ring oscillator, an LC oscillator, and a source-coupled ring oscillator. |
| Claim: | 15. The clock multiplier of claim 12 , wherein the delayed reference signal is delayed from the reference signal by about a half period of the oscillating signal. |
| Claim: | 16. The clock multiplier of claim 12 , wherein the oscillator circuit includes a coupler and a free-running oscillator, the coupler coupling both the reference clock and the delayed reference clock into the free-running oscillator to cause phase adjustments in the oscillating signal, the phase adjustments acting to pull the frequency of oscillating signal to the multiple of the frequency of the reference clock. |
| Claim: | 17. The clock multiplier of claim 16 , wherein the free-running oscillator is selected from a group consisting of an inverter ring oscillator, an LC oscillator, and a source-coupled ring oscillator. |
| Claim: | 18. The clock multiplier of claim 16 , wherein the coupler includes two pairs of field-effect transistors, each pair receiving a respective one of the reference clock and the delayed reference clock at a gate of each field-effect transistor in the pair. |
| Claim: | 19. The clock multiplier of claim 12 , wherein the oscillator circuit includes first and second oscillators each having a frequency controlled by the control signal, the first oscillator outputting the oscillating signal, the second oscillator being a replica of the first oscillator and a part of a loop circuit that adjusts the control signal so that the frequency of the second oscillator is N times the frequency of the reference clock. |
| Claim: | 20. A clock multiplier, comprising: a frequency multiplying circuit to receive a reference clock and to generate a clock signal having a frequency that is N times a frequency of the reference clock; and an oscillator circuit to filter the clock signal from the frequency multiplying circuit, the oscillator circuit reducing pulse width variations in the clock signal by making phase adjustments to spread each pulse width variation across a number of cycles of the clock signal. |
| Claim: | 21. The clock multiplier of claim 20 , wherein the number of cycles is N cycles. |
| Claim: | 22. The clock multiplier of claim 20 , wherein the oscillator circuit includes a coupler and a free-running oscillator, the free-running oscillator outputting a filtered clock signal, the coupler having an adjustable strength that determines the number of cycles. |
| Claim: | 23. The clock multiplier of claim 22 , wherein the strength of the coupler is adjusted so that a phase of the filtered clock signal catches up with a phase of the clock signal from one adjustment to a next adjustment. |
| Claim: | 24. The clock multiplier of claim 22 , wherein the coupler acts to gradually bring the filtered clock signal back in phase with the clock signal over the number of cycles. |
| Claim: | 25. The clock multiplier of claim 20 , wherein number of cycles is larger than N and the oscillator circuit further filters jitter in the reference clock that are passed to the clock signal. |
| Current U.S. Class: | 331/172 |
| Patent References Cited: | 4347484 August 1982 Vandegraaf 4355404 October 1982 Uzunoglu 5172357 December 1992 Taguchi 5563554 October 1996 Mizuno 5708381 January 1998 Higashisaka 6025756 February 2000 Miyabe 6188291 February 2001 Gopinathan et al. 6256361 July 2001 Mozetic et al. 6317008 November 2001 Gabara 6617936 September 2003 Dally et al. 6861916 March 2005 Dally et al. 6924705 August 2005 Huang 7078979 July 2006 Dally et al. |
| Other References: | Rategh, H.R., et al., “Superharmonic Injection Locked Oscillators as Low Power Frequency Dividers,” Symposium of VLSI Circuits Digest of Technical Papers, pp. 132-135, (1998). cited by other Rategh, H.R., et al., “Superharmonic Injection-Locked Frequency Dividers,” IEEE Journal of Solid-State Circuits, 34(6): 813-821 (Jun. 1999). cited by other Wong, K.W., et al., “Phase Tuning Beyond 180 Degrees by Injection-Locked Oscillators,” IEEE TENCON '93/Beijing, pp. 1-4 (1993). cited by other Wong, K.W., et al., “Frequency Synthesis Using Non-Integral Subharmonic Injection Locking,” IEEE TENCON '93/Beijing, pp. 16-19 (1993). cited by other Tokumitsu, T., et al., “A Novel Injection-Locked Oscillator MMIC with Combined Ultrawide-Band Active Combiner/Divider and Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, 42(12): 2572-2578 (Dec. 1994). cited by other |
| Primary Examiner: | Mis, David |
| Attorney, Agent or Firm: | Hamilton, Brook, Smith & Reynolds, P.C. |
| رقم الانضمام: | edspgr.07414489 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |