Patent
Self-aligned method for defining a semiconductor gate oxide in high voltage device area
| العنوان: | Self-aligned method for defining a semiconductor gate oxide in high voltage device area |
|---|---|
| Patent Number: | 7,253,114 |
| تاريخ النشر: | August 07, 2007 |
| Appl. No: | 11/082514 |
| Application Filed: | March 16, 2005 |
| مستخلص: | A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure. |
| Inventors: | Chen, Chien-Mao (Kaohsiung, TW); Liu, Jun Xiu (Taichung, TW); Huang, Cuker (Banciao, TW); Chang, Chi-Hsuen (Hsinchu, TW) |
| Assignees: | Taiwan Semiconductor Manufacturing Company (Hsin-Chu, TW) |
| Claim: | 1. A method for forming a semiconductor device comprising: providing a substrate with designated high voltage (HV) and low voltage (LV) areas; forming a plurality of gate oxides including a thick gate oxide in said HV area and at least one thin gate oxide in said LV area, said thick gate oxide being thicker than said at least one thin gate oxide; forming a pattern of poly features in each of said high voltage and low voltage areas, said poly features including polysilicon covered by an etch resistant material; forming a photoresist pattern at least over said LV area; plasma etching to remove said thick gate oxide from said HV area that is not masked by one of said poly features; removing said photoresist pattern; and wet etching to remove said at least one thin gate oxide from said LV area not masked by one of said poly features. |
| Claim: | 2. The method as in claim 1 , wherein said etch resistant material comprises silicon oxynitride. |
| Claim: | 3. The method as in claim 1 , wherein each of said plurality of gate oxides is formed by thermally oxidizing after patterning with a silicon nitride film. |
| Claim: | 4. The method as in claim 1 , further comprising, prior to said wet etching, forming a further photoresist pattern over said HV area. |
| Claim: | 5. The method as in claim 1 , wherein said wet etching comprises exposing said substrate to a hydrofluoric acid solution. |
| Claim: | 6. The method as in claim 1 , further comprising forming a high voltage transistor using one of said poly features and said thick gate oxide, forming a low voltage transistor using one of said poly features and said thin gate oxide, operating said high voltage transistor at a voltage greater than 20 volts and operating said low voltage transistor at a voltage within a range of 1.5-5 volts. |
| Claim: | 7. The method as in claim 6 , wherein said first thin gate oxide includes a thickness less than 150 angstroms, and said thick gate oxide includes a thickness greater than 300 angstroms. |
| Claim: | 8. The method as in claim 1 , wherein said at least one thin gate oxide comprises a first thin gate oxide and a second thin gate oxide, said forming a pattern of poly features includes forming said poly features over said first thin gate oxide and over said second thin gate oxide; and said wet etching removes said first thin gate oxide and said second thin gate oxide in areas not masked by one of said poly features. |
| Claim: | 9. The method as in claim 8 , wherein said first thin gate oxide includes a thickness less than 40 angstroms, said second thin gate oxide includes a thickness within a range of 100-200 angstroms and said thick gate oxide includes a thickness greater than 300 angstroms. |
| Claim: | 10. The method as in claim 8 , further comprising forming a first transistor using one of said poly features and said first thin gate oxide, forming a second transistor using one of said poly features and said second thin gate oxide, and forming a third transistor using one of said poly features and said thick gate oxide and operating said first transistor at an operating voltage of 1.8-2.5 volts, operating said second transistor at an operating voltage of about 4-6 volts, and operating said third transistor at an operating voltage greater than 30 volts. |
| Claim: | 11. The method as in claim 8 , further comprising forming a protective material over said HV area prior to said wet etching. |
| Claim: | 12. The method as in claim 1 , wherein said plasma etching includes a pressure within a range of 30-50 millitorr and includes at least CHF 3 , O 2 and CO as etch gases. |
| Claim: | 13. The method as in claim 1 , wherein said etch resistant material prevents said polysilicon from being attacked during said plasma etching. |
| Claim: | 14. A method for forming a semiconductor device comprising: providing a substrate with designated high voltage (HV) and low voltage (LV) areas; forming a plurality of gate oxides including at least one thick gate oxide in said HV area and at least one thin gate oxide in said LV area, each thick gate oxide being thicker than each thin gate oxide; forming a pattern of poly features in each of said high voltage and low voltage areas, said poly features including polysilicon covered by a hardmask; plasma etching to remove said at least one thick gate oxide from said HV area that is not masked by a hardmask; and wet etching to remove said at least one thin gate oxide from said LV area not masked by one of said poly features. |
| Claim: | 15. The method as in claim 14 , further comprising forming a photoresist pattern at least over said LV area prior to said plasma etching and forming a further photoresist pattern over said HV area prior to said wet etching. |
| Claim: | 16. A method for forming a semiconductor device comprising: providing a substrate with designated high voltage (HV) and low voltage (LV) areas; forming a plurality of gate oxides including at least one thick gate oxide in said HV area and at least one thin gate oxide in said LV area, each thick gate oxide being thicker than each thin gate oxide; forming masking patterns over said plurality of gate oxides, said masking patterns including patterned photoresist sections and poly features including polysilicon covered by a hardmask; plasma etching using a selective oxide etch that removes portions of said plurality of gate oxides not covered by said masking patterns; removing said patterned photoresist sections; and wet etching to remove portions of said at least one thin gate oxide from areas not masked by one of said poly features. |
| Claim: | 17. The method as in claim 16 , in which said patterned photoresist sections are formed over said LV area and further comprising, after said removing said patterned photoresist sections, forming photoresist at least over said HV area and performing said wet etching with said photoresist at least over said HV area. |
| Claim: | 18. The method as in claim 17 , in which said forming masking patterns includes forming said poly features over said at least one thick gate oxide in said HV area and forming said poly features over said at least one thin gate oxide in said LV area and wherein said patterned photoresist sections are formed over said poly features formed over said at least one thin gate oxide in said LV area. |
| Claim: | 19. The method as in claim 16 , wherein said at least one thin gate oxide comprises a first thin gate oxide and a second thin gate oxide, said forming masking patterns includes said poly features formed over said first thin gate oxide, over said second thin gate oxide and over a thick gate oxide of said at least one thick gate oxide; further comprising forming a first transistor over said first thin gate oxide, forming a second transistor over said second thin gate oxide and forming a third transistor over said thick gate oxide; and operating said first transistor at an operating voltage of 1.8-2.5 volts, operating said second transistor at an operating voltage of about 4-6 volts, and operating said third transistor at an operating voltage greater than 30 volts. |
| Claim: | 20. The method as in claim 19 , wherein said first thin gate oxide includes a thickness less than 40 angstroms, said second thin gate oxide includes a thickness within a range of 100-200 angstroms and said thick gate oxide includes a thickness greater than 300 angstroms. |
| Current U.S. Class: | 438/704 |
| Patent References Cited: | 5827784 October 1998 Loos 6281050 August 2001 Sakagami 2004/0026750 February 2004 Takamura 2004/0266111 December 2004 Lee |
| Assistant Examiner: | Garcia, Joannie Adelle |
| Primary Examiner: | Fourson, George |
| Attorney, Agent or Firm: | Duane Morris LLP |
| رقم الانضمام: | edspgr.07253114 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |