Patent
System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
| العنوان: | System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored |
|---|---|
| Patent Number: | 6,968,469 |
| تاريخ النشر: | November 22, 2005 |
| Appl. No: | 09/595198 |
| Application Filed: | June 16, 2000 |
| مستخلص: | A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption. |
| Inventors: | Fleischmann, Marc (Menlo Park, CA, US); Anvin, H. Peter (San Jose, CA, US) |
| Assignees: | Transmeta Corporation (Santa Clara, CA, US) |
| Claim: | 1. A method of reducing electrical power consumption by a digital computer when said digital computer is supplied with electrical power, but fails to process a computer application program for a prescribed period of inactivity, said digital computer including a host processor, said method comprising the computer implemented steps of: said host processor producing and maintaining an internal context, said host processor containing code morphing software for dynamically translating and executing target applications designed for execution by a target processor, whereby said host processor creates a virtual target processor, said host processor maintaining data representing the state of said virtual target processor during processing of instructions of a target application and said internal context of said virtual target processor, said digital computer also including a private memory for storing at least the state of said virtual target processor and target application and said internal context of said virtual target processor; determining if said prescribed period of inactivity has been attained, and, in response to an affirmative determination; preserving said internal context of said virtual target processor against loss due to removal of electrical power from said host processor, said internal context of said virtual target processor preserved in said private memory, wherein said private memory is accessible only by said host processor and powered independently of said host processor; producing a signature in response to said determining to indicate that said private memory contains information; removing all electrical power from said host processor, whereby said host processor is powered down, notwithstanding continued supply of electrical power to said digital computer; and restoring electrical power to said host processor and restoring said preserved internal context of said virtual target processor to said host processor when processing is to resume. |
| Claim: | 2. The method defined in claim 1 , wherein said step of preserving said internal context of said virtual target processor against loss due to removal of electrical power from said host processor, includes: reading said internal context of said virtual target processor from the internal memory of said host processor prior to removal of electrical power from said host processor, said internal memory comprising internal registers; and writing said internal context of said virtual target processor into said private memory. |
| Claim: | 3. The method as defined in claim 1 wherein said host processor includes a cache memory; and wherein said step of preserving said internal context of said virtual target processor, includes: supplying electrical power to said cache memory separately from said host processor, wherein removal of electrical power from said host processor leaves electrical power to said cache memory unaffected to prevent loss of said internal context of said host processor on removal of electrical power from said host processor. |
| Claim: | 4. The method as defined in claim 1 , wherein the step of restoring electrical power to said host processor and restoring said preserved internal context of said virtual target processor to said host processor when processing is to resume, further comprises: initializing said host processor; determining whether application of electrical power was due to a power on reset condition or a resume from a suspend to RAM condition; and upon determining that electrical power commenced due to a resume from a suspend to RAM condition, then accessing and installing said preserved internal context of said virtual target processor to said host processor. |
| Claim: | 5. The method as defined in claim 1 , wherein said step of restoring electrical power to said host processor and restoring said preserved internal context of said virtual target processor to said host processor when processing is to resume, further comprises: initializing said host processor; determining whether restoration of electrical power to said host processor is due to a power on reset condition or a resume from a suspend to RAM condition; and upon determining that electrical power commenced due to a resume from a suspend to RAM condition, then accessing said preserved internal context of said virtual target processor in said private memory and reading back said internal context of said virtual target processor into internal registers of said host processor for access by said host processor, whereby said internal context of said virtual target processor of said host processor is restored. |
| Claim: | 6. A processing system, comprising: a central processing unit (CPU) for processing instructions of an application, said central processing unit including internal registers; a first memory; a second memory accessible only to said CPU; a power supply for supplying power separately to said CPU and said first and second memories, wherein said CPU, said first memory and said second memory each reside in separate power domains; said power supply including: a rechargeable battery; first power circuit means for distributing electrical power to said CPU; second power circuit means for distributing electrical power to at least said first memory and said second memory; and an on-off switch for closing power from said battery to each of said first and second power circuit means, whereby said first and second power circuit means are enabled to deliver power; first program routine means for detecting inactivity of application instruction processing of said CPU for a period of time, Tmax; second program routine means for saving the internal context of said CPU in said second memory and for producing a signature in response to a positive detection of inactivity by said first program routine means, said signature indicating that said second memory contains information; third program routine means for terminating distribution of power by said first power circuit means following completion of said second program routine means, whereby power is removed from said CPU while said internal context of said CPU is preserved in said second memory. |
| Claim: | 7. The processor as defined in claim 6 , further comprising: a user operated input device for enabling user input to said application; means for enabling said second power circuit means to distribute power to said CPU, responsive to operation of said user operated input device; program means responsive to re-energization of said CPU for initiating an initialization process for said CPU; loading and processing a boot loader; configuring internal memory of said CPU, excluding said second memory; resetting registers of said CPU; and checking for said signature; fourth routine program means, responsive to detection of said signature, for retrieving the portion of said internal context of said CPU earlier stored in said internal memory of said CPU and reading back said portion of said internal context of said CPU into the internal registers of said CPU, and retrieving said context of said Northbridge registers and loading said context of said Northbridge registers in said internal memory of said CPU. |
| Claim: | 8. The processor as define in claim 7 , further comprising: fifth routine program means for retrieving the next instruction of the application program for execution by said CPU, responsive to completion of said fourth routine program means. |
| Claim: | 9. A processing system, comprising: a central processing unit for processing instructions, said central processing unit including internal registers; a first memory; a second memory accessible only to said central processing unit; code morphing program means defining a virtual X86 processing system, said virtual X86 processing system including a virtual X86 central processing unit and a virtual Northbridge chip, whereby instructions of an X86 application may be processed in said processing system; a power supply for supplying power separately to said CPU and said first and second memories, wherein said CPU, said first memory and said second memory each reside in separate power domains; said power supply including: a rechargeable battery; first power circuit means for distributing electrical power to said CPU; second power circuit means for distributing electrical power to at least said first and second memory; and an on-off switch for closing power from said battery to each of said first and second power circuit means, whereby said first and second power circuit means are enabled to deliver power; first program routine means for detecting inactivity of application instruction processing of said CPU for a period of Tmax; second program routine means for saving the entire internal context of said CPU in said second memory and for producing a signature in response to a positive detection of inactivity by said first program routine means, said signature indicating that said second memory contains information; third program routine means for terminating distribution of power by said first power circuit means following completion of said second program routine means, whereby power is removed from said CPU and said CPU is placed in an off state while said internal context of said CPU is preserved in said second memory. |
| Claim: | 10. The processor as defined in claim 9 , further comprising: means for enabling said second power circuit mean distribute power to said CPU, responsive to operation of said user operated input device; program means responsive to re-energization of said CPU for initiating an initialization process for said CPU; loading and processing a boot loader; configuring internal memory of said CPU, excluding said second memory; resetting the registers of said CPU; and checking for said signature; fourth program routine means, responsive to detection of said signature, for retrieving the portion of said internal context of said CPU earlier stored in one of said first and second memory and reading back said portion into the internal registers of said CPU, and retrieving said context of said Northbridge registers earlier stored in one of said first and second memory and loading said context in said internal registers of said CPU. |
| Claim: | 11. A digital computer comprising: a CPU; a private memory accessible only by said CPU; and a power supply, said power supply for supplying power to said CPU and said private memory independent of one another to enable withdrawal of power from said CPU without withdrawal of power from said private memory; said CPU defining and maintaining a CPU context to enable processing of application programs; said CPU containing code morphing software for dynamically translating and executing target applications designed for execution by a target processor, whereby said CPU creates a virtual target processor, said CPU maintaining data representing the state of said virtual target processor during processing of instructions of a target application and said internal context of said virtual target processor; said private memory for storing at least the state of said virtual target processor and said target application, said internal context of said virtual target processor and said CPU context, whereby said CPU context is retained upon withdrawal of power from said CPU without withdrawal of power from said private memory and wherein a flag is set to indicate that said private memory contains said CPU context. |
| Claim: | 12. A method of reducing power consumption of a digital computer during a sleep mode of operation, said digital computer including a power management program for placing said digital computer in multiple stages of sleep mode, said multiple stages of sleep comprising at least a pre-STR (suspend to RAM) stage and an STR stage, said method comprising: determining whether a first instruction is issued said power management program for placing said digital computer in a pre-STR stage of sleep, said pre-STR stage comprising maintaining power to a processor of said digital computer; intercepting said first instruction; and substituting for said first instruction a second instruction to place said digital computer in said STR stage of sleep, said STR stage comprising removing power from said processor, wherein entry to said STR stage occurs bypassing said pre-STR stage in response to said first instruction and transparent to said power management program. |
| Claim: | 13. The method of claim 12 further comprising: writing internal context of said processor to a private memory accessible only by said processor and powered independently of said processor; and removing power from said processor. |
| Claim: | 14. A computer system comprising: a processor; a first memory accessible by said processor; a second memory accessible only to said processor, wherein said second memory is internal to said processor, wherein power to said second memory is controlled separately from power to said processor and to said first memory, wherein power is maintained to said second memory when power is removed from said processor, said second memory for maintaining internal context of said processor when power is removed from said processor; and a third memory external to said processor and accessible only to said processor, wherein power to said third memory is controlled separately from power to said processor and to said first and second memories. |
| Current U.S. Class: | 713/324 |
| Patent References Cited: | 4523206 June 1985 Sasscer 4763333 August 1988 Byrd 5204963 April 1993 Noya et al. 5617572 April 1997 Pearce et al. 5671229 September 1997 Harari et al. 5765001 June 1998 Clark et al. 5864659 January 1999 Kini 5878264 March 1999 Ebrahim 5898880 April 1999 Ryu 5935259 August 1999 Anderson 5991531 November 1999 Song et al. 6035407 March 2000 Gebara et al. 6182231 January 2001 Gilgen 6266776 July 2001 Sakai 6397242 May 2002 Devine et al. 6405320 June 2002 Lee et al. 6484274 November 2002 Lee et al. |
| Other References: | Tanenbaum, Andrew; 1984, “Structured Computer Organization”, Prentice-Hall inc., 2nd Ed., p. 11. cited by examiner |
| Assistant Examiner: | Connolly, Mark |
| Primary Examiner: | Lee, Thomas |
| Attorney, Agent or Firm: | Wagner, Murabito & Hao LLP |
| رقم الانضمام: | edspgr.06968469 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |