Patent
Video/graphics memory system
| العنوان: | Video/graphics memory system |
|---|---|
| Patent Number: | 6,091,429 |
| تاريخ النشر: | July 18, 2000 |
| Appl. No: | 09/189,168 |
| Application Filed: | November 09, 1998 |
| مستخلص: | A video/graphics memory system includes a memory device (30) having a memory core (14) and first and serial registers (16, 36). The memory device thus has a random-access port (24) for graphics data, a first serial access port (22) for image output to a display, and an auxiliary or second serial port (32) for input and output of video signal data. A single memory thus stores both video and graphics data, while the processor still has access to the random access port of the memory. Two video outputs can be provided simultaneously, or the data withdrawn through the auxiliary port can be subject to processing and then written back into the memory. In alternative arrangements, instead of using triple-ported RAM, the auxiliary port is provided by the use of external multiplexing circuitry. |
| Inventors: | Yassaie, Hossein (Chesham, GBX); Metcalfe, John Anthony (Dunstable, GBX); Deacon, Graham (Hemel Hempstead, GBX); Ashton, Martin (Berkhampsted, GBX) |
| Assignees: | Imagination Technologies Limited (Kings Langley, GBX) |
| Claim: | We claim |
| Claim: | 1. A video/graphics system comprising a processor for generating graphics data and mask data, a video signal port for receiving video data, a display signal output port over which an integrated stream of video data and graphics data are output and a memory means, said memory means including |
| Claim: | at least one random access memory with multiple image data locations, said image data locations being able to selectively store both graphics data from said processor and video data, a first random access port and a mask plane connected to said processor for receiving and storing the mask data; |
| Claim: | a second random access port selectively coupled to said first random access port for connecting said random access memory to said processor for the transfer of graphics data to said random access memory; |
| Claim: | a serial access port connecting said random access memory to said display signal output port for transfer of video data and graphics data to said display signal output port for forwarding to an external display; |
| Claim: | an auxiliary port connecting said video signal port to said random access memory for transfer of video data to said random access memory; |
| Claim: | masked write control means for receiving mask data from said mask plane and for controlling the overwriting of data into said data locations of said random access memory based on the mask data; and |
| Claim: | inhibiting means attached to said masked write control means for inhibiting the incorrect use of mask data in said masked write control means if the mask data in said mask plane has been altered. |
| Claim: | 2. The video/graphics system of claim 1, wherein |
| Claim: | said processor generates the mask data as part of said generation of the graphics data and transfers the mask data to said mask plane as said graphics data are generated; and |
| Claim: | said inhibiting means includes means for determining if, when the graphics data are being generated, the mask data are being generated and means for blocking the transfer of video data to said auxiliary port when the mask data are being generated with the graphics data. |
| Claim: | 3. The video/graphics system of claim 1, wherein |
| Claim: | said mask plane includes a plurality of addressable mask data locations that correspond to said image data locations; |
| Claim: | said processor simultaneously writes graphics data into said image data locations and mask data into said mask data locations that correspond with said image data location to which the graphics data is written; |
| Claim: | said inhibiting means includes conflict evaluator means for determining if said processor is attempting to write graphics data into a set of said image data locations while video data are being written into said set of image data locations, and means for preventing said processor from writing graphics data into said set of said image data locations if said conflict evaluator means determines video data are being written into said set of image data locations. |
| Claim: | 4. The video/graphics system of claim 1, wherein |
| Claim: | said processor simultaneously writes graphics data into said image data locations and mask data into said mask data locations that correspond with said image data location to which the graphics data is written; and |
| Claim: | said inhibiting means includes conflict evaluator means for determining if the video data are being provided to said random access memory for writing into a set of said image data locations while said processor is writing graphics data into said set of said image data locations and means for preventing the video data from being written into said set of said image data locations if said conflict evaluator means determines the graphics data are being written into said set of image data locations. |
| Claim: | 5. The apparatus of claim 1, wherein |
| Claim: | said processor simultaneously generates graphics data for a specific image data location and mask data for a corresponding mask data location; and |
| Claim: | said inhibiting means comprises a delay means for delaying when the graphics data are written into said specific image data location until after the mask data are written in said corresponding image data location. |
| Current U.S. Class: | 345/509; 345/518 |
| Current International Class: | G09G 336 |
| Patent References Cited: | 4165072 August 1979 Stubben 4257043 March 1981 Tsuchiko 4297694 October 1981 Matherat 4471348 September 1984 London et al. 4812836 March 1989 Kurakake et al. 4825411 April 1989 Hamano 4891631 January 1990 Fredlund et al. 5001671 March 1991 Koo et al. 5027212 June 1991 Marlton et al. 5220312 June 1993 Lumelsky et al. 5231383 July 1993 Diepstraten et al. 5274753 December 1993 Roskowski et al. 5402147 March 1995 Chen et al. |
| Other References: | IRE Wescon Conference Record, vol. 34, Nov. 1990, North Hollywood, CA, US, pp. 18-23, "Multiport DRAM Trends". Micron Technology, Inc., Triple Port DRAM', MT43C4257/8, Jan. 1991, pp. 1-6. Electronic Design, May 24, 1990, San Jose, CA, "Triple-Port Dynamic Ram Accelerates Data Movement", Dave Bursky, 3 pages. |
| Primary Examiner: | Mengistu, Amare |
| Attorney, Agent or Firm: | Flynn, Thiel, Boutell & Tanis, P.C. |
| رقم الانضمام: | edspgr.06091429 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |