Patent
Method for transferring a multi-level photoresist pattern
| العنوان: | Method for transferring a multi-level photoresist pattern |
|---|---|
| Patent Number: | 6,043,164 |
| تاريخ النشر: | March 28, 2000 |
| Appl. No: | 08/665,014 |
| Application Filed: | June 10, 1996 |
| مستخلص: | A method is provided for forming an intermediate level in an integrated circuit dielectric during a damascene process using a photoresist mask having an intermediate thickness. The method forms an interconnect to a first depth in the dielectric through an opening in the photoresist pattern. The photoresist profile is partially etched away in the area of the intermediate thickness to reveal a second dielectric surface area. The second dielectric surface area is then etched to a second depth less than the first depth. In this manner, vias can be formed to the first depth, and lines can be formed at a second depth to intersect the vias. The method of the present invention allows a dual damascene process to be performed with a single step of photoresist formation. |
| Inventors: | Nguyen, Tue (Vancouver, WA); Hsu, Sheng Teng (Camas, WA); Maa, Jer-shen (Vancouver, WA); Ulrich, Bruce Dale (Beaverton, OR); Peng, Chien-Hsiung (Vancouver, WA) |
| Assignees: | Sharp Laboratories of America, Inc. (Camas, WA) |
| Claim: | What is claimed is |
| Claim: | 1. In an integrated circuit wafer including levels of integrated circuit material having a surface, a method of forming electrical interconnects from the surface to a plurality of interlevels in the integrated circuit material, comprising the steps of |
| Claim: | a) forming a single bi-level resist profile over the surface, the resist profile having a plurality of thicknesses and openings, with one thickness an opening to form an interconnect line, and a second thickness an opening through the resist profile to reveal an integrated circuit material surface area to form a via, the opening for the interconnect line intersecting the opening for the via; |
| Claim: | b) removing integrated circuit material underlying the opening in the resist profile formed in step a); |
| Claim: | c) after Step b), removing a portion of the resist profile to form an opening revealing a second integrated circuit surface area; and |
| Claim: | d) removing integrated circuit material underlying the opening formed in step c), whereby integrated circuit material is removed to generally reproduce the shape of the overlying resist profile. |
| Claim: | 2. The method as in claim 1 in which the resist profile formed in step a) has a first and second thickness, with the second thickness greater than the first thickness, and in which steps b) and d) include the removal of integrated circuit material to two interlevels with a first interlevel underlying the opening formed in step a), and a second interlevel underlying the opening formed in step c), so that the second interlevel is closer to the surface than the first interlevel. |
| Claim: | 3. The method as in claim 2 in which step b) includes the removal of integrated circuit material, underlying the opening formed in step a), to an interlevel, and in which step d) includes the removal of integrated circuit material underlying the opening formed in step c) to the second interlevel, and the further removal of integrated circuit material underlying the opening formed in step a), from the interlevel of step b), to the first interlevel. |
| Claim: | 4. The method as in claim 3 in which the wafer has connection areas in the integrated circuit material at two interlevels, and in which steps b) and d) include the removal of integrated circuit material to three interlevels. |
| Claim: | 5. The method as in claim 4 in which step b) includes the removal of integrated circuit material to form a via to a second connection area at a second interlevel, and in which step d) includes the further removal of integrated circuit material, from integrated circuit material removed in step b), to form a via to a first connection area at a first interlevel, and in which step d) further includes the removal of integrated circuit material to form a trench underlying the opening formed in step c). |
| Claim: | 6. The method as in claim 5 including the further steps, following step d), of |
| Claim: | e) removing the remaining resist profile, left overlying the surface; |
| Claim: | f) depositing a conductive material in the areas of the wafer where integrated circuit material is removed in steps b) and d) to form electrical interconnect vias to the first and second connection areas from the surface, and depositing a conductive material in the trench formed in step d) to form a line between the third interlevel and the surface; and |
| Claim: | g) polishing the surface, including the filled conductive interconnects to form a planar surface having a flatness, whereby electrical connections are made to the surface from multiple levels in the wafer. |
| Claim: | 7. The method as in claim 1 in which the etching of step b) is performed using an etchant chosen to minimize the production of polymer by-products. |
| Claim: | 8. The method as in claim 1 in which the conductive material used in the interconnects is selected from the group consisting of CVD copper and tungsten, and the integrated circuit material is selected from the group consisting of silicon dioxide, TEOS oxide, silane oxide, BN, and nitride. |
| Claim: | 9. The method as in claim 1 in which the width of the opening formed through the resist profile in step a) is less than 5 .mu.m, and in which steps b) and d) include forming a via having a width less than 5 .mu.m. |
| Claim: | 10. The method as in claim 1 in which the etching in step c) is performed with an anisotropic plasma etch. |
| Claim: | 11. The method as in claim 10 in which the anisotropic plasma etch consisting of oxygen. |
| Claim: | 12. The method as in claim 1 in which step b) is performed by etching using a gas selective with regards to a dielectric as opposed to the underlying wafer material. |
| Claim: | 13. The method as in claim 2 including the further step, before step a), of forming a sacrificial buffer layer, having a thickness, over the integrated circuit material surface, the buffer layer having a removal selectivity different from the resist profile and integrated circuit material, whereby the resist profile and buffer layer control the removal of integrated circuit material. |
| Claim: | 14. The method as in claim 13 in which the wafer has connection areas at two interlevels, and in which the integrated circuit material is removed to three interlevels in step b). |
| Claim: | 15. The method as in claim 14 in which step b) includes the removal of the buffer layer underlying the opening in the resist profile formed in step a) to reveal the integrated circuit material surface area, and removing the integrated circuit material surface area to form a via to an interlevel, in which step c) includes revealing an area of buffer layer, in which step d) includes the removal of the buffer layer area underlying the opening in the resist profile formed in step c), in which step d) further includes the further removal of integrated circuit material from the area underlying the opening formed in step a) to form vias to a first connection area on a first interlevel and a second connection area on a second interlevel, and in which step d) further includes the removal of integrated circuit material underlying the opening formed in step c) to form a trench from the surface to a third interlevel. |
| Claim: | 16. The method as in claim 13 wherein the removed integrated circuit material is selected from the group consisting of silicon dioxide, TEOS oxide, silane oxide, BN, and nitride, and in which the sacrificial buffer layer is selected from the group consisting of silicon, metal, semiconductor, and dielectrics having a different removal selectivity from adjacent integrated circuit material. |
| Claim: | 17. The method as in claim 3 wherein the wafer has connection areas in the integrated circuit at three or more interlevels, and in which steps b) and d) include the removal of integrated circuit material to four or more interlevels. |
| Claim: | 18. In an integrated circuit interlevel dielectric including integrated circuit material having a surface, a method of etching the integrated circuit material comprising the steps of |
| Claim: | a) forming a single bi-level photoresist pattern overlying the integrated circuit surface, the resist pattern having a plurality of thicknesses and openings, with a first thickness an opening to form an interconnect line, and a second thickness an opening through the photoresist to expose an integrated circuit material surface area to form a via intersecting the interconnect line; |
| Claim: | b) etching the exposed integrated circuit material surface area; |
| Claim: | c) after Step b), etching part of the photoresist to create an opening, exposing a second integrated circuit material surface area, and leaving part of the photoresist over the integrated circuit material surface; and |
| Claim: | d) repeating step b) to etch the integrated circuit material surface exposed in step c), and to further etch the integrated circuit material initially etched in step b), whereby the integrated circuit material is etched to generally reproduce the shape of the photoresist pattern. |
| Claim: | 19. The method as in claim 18 in which steps c) and d) are repeated a plurality of times, whereby the integrated circuit material is etched to a plurality of levels from the surface. |
| Claim: | 20. The method as in claim 18 in which the photoresist pattern has two thicknesses with the second thickness greater than the first thickness, and in which step c) includes etching a layer having a thickness greater than the photoresist pattern first thickness to expose the second integrated circuit material surface area. |
| Claim: | 21. The method as in claim 18 in which the etching of step b) is performed using an etchant chosen to minimize the production of polymer by-products. |
| Claim: | 22. The method as in claim 18 in which the photoresist is etched in step c) with an anisotropic plasma etch. |
| Claim: | 23. The method as in claim 18 in which the anisotropic plasma etch consists of oxygen. |
| Claim: | 24. The method as in claim 18 in which the width of the opening formed through the resist profile in step a) is less than 5 .mu.m, and in which steps b) and d) include forming a via having a width less than 5 .mu.m. |
| Claim: | 25. The method as in claim 18 in which the etching of step b) is performed using a gas selective with regards to the dielectric as opposed to the underlying wafer material. |
| Claim: | 26. The method as in claim 18 wherein electrical interconnects are formed from the surface to areas in the integrated circuit material, and including the further steps, following step d), of |
| Claim: | e) stripping, to completely remove from the surface, any photoresist remaining after step d); |
| Claim: | f) depositing a conductive material where integrated circuit material is removed in steps b) and d). |
| Claim: | 27. A method for transferring a photoresist pattern onto an integrated circuit interlevel dielectric including an oxide layer having interlevels and a surface, the oxide layer overlying a silicon layer, the method comprising the steps of |
| Claim: | a) forming a single photoresist pattern overlying the surface, the photoresist pattern having two thicknesses with the second thickness greater than the first thickness, the photoresist having an opening through the photoresist second thickness to expose an integrated circuit material surface area to form a via and an intersecting opening through the photoresist first thickness to form a trench, the photoresist having an etch selectivity different than the oxide; |
| Claim: | b) etching the integrated circuit surface area exposed in step a) with C.sub.2 F.sub.6 to begin a via hole in the oxide; |
| Claim: | c) after Step b), etching the photoresist at a temperature between 10.degree. C. and -10.degree. C. to remove a layer across the photoresist greater than the first thickness, but less than the second thickness, the photoresist being etched to expose a second integrated circuit material surface area; and |
| Claim: | d) etching, with C.sub.3 F.sub.8, the second integrated circuit material surface area exposed in step c) to form a trench in the oxide from the surface to a interlevel in the oxide, and further etching the via hole begun in step b) to form a hole through the oxide to the silicon layer, whereby the photoresist is selectively etched to from a multi-level damascene pattern in the oxide. |
| Current U.S. Class: | 438/736; 438/738; 438/717; 438/782; 430/312; 430/323 |
| Current International Class: | H01L 21302 |
| Patent References Cited: | 5225035 July 1993 Rolfson 5237393 August 1993 Tominaga 5308721 May 1994 Garofalo et al. 5328807 July 1994 Tanaka et al. 5358827 October 1994 Garofalo et al. 5384218 January 1995 Tokui et al. 5384219 January 1995 Dao et al. 5414746 May 1995 Deguchi et al. 5426010 June 1995 Morton 5446521 August 1995 Hainsey et al. 5460908 October 1995 Reinberg 5477058 December 1995 Sato 5635337 June 1997 Bartha et al. 5635423 June 1997 Huang et al. 5738757 April 1998 Burns et al. 5741624 April 1998 Jeng et al. 5753417 May 1998 Ulrich 5821169 October 1998 Nguyen et al. |
| Other References: | Article entitled, "Fabrication of 64M Dram with i-Line Phase-Shift Lithography" by K. Nakagaw, M. Taguchi and T. Ema printed in the IEDM 90-817, 1990 IEEE, pp 33.1.1-33.1.4. Article entitled, "Transparent Phase Shifting Mask", by H. Watanabe, Y. Todokoro, and M. Inoue, printed in the IEMM 90-821, 1990 IEEE, pp 33.2.1-33.2.4. Article entitled, "The Control of Sidelobe Intensity with Arrangement of the Chrome Pattern (COSAC) in Half-Tone Phase-Shifting Mask", by S. Kobayashi, N. Oka, K. Watanabe, M. Inoue and K. Sakiyama, reprinted from Extended Abstracts of 1995 Int'l Conference on Solid State Devices and Materials, Aug. 1995, pp 935-937. Article entitled, "Improving Resolution in Photolithography with a Phase-Shifting Mask", by M. Levenson, N.S. Viswanathan and R. Simpson, printed in the IEEE Transactions on Electron Devices, vol. ED-29, No. 12, Dec. 1982. Article entitled, "Phase Masks and Grey-Tone Masks", by Pierre Sixt, Litomask by SCEM, Neuchatel, Switzerland, printed in Semiconductor Fabtech, Issue No. 2, 1995, pp 209-213. |
| Primary Examiner: | Tsai, Jey |
| Assistant Examiner: | Gurley, Lynne A. |
| Attorney, Agent or Firm: | Ripma, David C. Rabdau, Mathew D. |
| رقم الانضمام: | edspgr.06043164 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |