Patent
Microcomputer development system
| العنوان: | Microcomputer development system |
|---|---|
| Patent Number: | 4,847,805 |
| تاريخ النشر: | July 11, 1989 |
| Appl. No: | 06/892,036 |
| Application Filed: | August 01, 1986 |
| مستخلص: | A development system for a family of one-chip microcomputers which are all of the same architecture but differ in the memory size and the input/output number, comprises a common emulation chip having the largest memory size and the largest input/output number in the microcomputer family, an information memory storing a data memory area utilizable in a target microcomputer to be developed, a local emulation chip for emulating the peripheral hardware of the target microcomputer, and a guard controller generating a guard verify signal for stopping an emulation operation when the access is made to a memory area or a peripheral hardware which is not to be included in the target microcomputer. Thus, the access to the resources which is not to be included in the target microcomputer is inhibited. |
| Inventors: | Ishii, Yasunori (Tokyo, JPX); Yura, Mamoru (Tokyo, JPX) |
| Assignees: | NEC Corporation (Tokyo, JPX) |
| Claim: | We claim |
| Claim: | 1. A microcomputer development system for a family of microcomputers having a same architecture but differing in resources, the system comprising |
| Claim: | an emulation memory storing a program for a target microcomputer, said program to be emulated; |
| Claim: | an emulation chip, coupled to the emulation memory in an emulation mode, for executing emulation of the program stored in the emulation memory in an emulation mode; |
| Claim: | an information memory for storing information indicating a resource which can be used by the target microcomputer; |
| Claim: | a guard controller, connected to said information memory, for copying a content of the information memory in a supervisor mode before the emulation chip starts to execute the program, stored in the emulation memory, in the emulation mode, the guard controller, in the emulation mode, comparing information written in the guard controller with address information from the emulation chip so as to generate and send a guard verify signal when the address information indicates access to a resource which cannot be used by the target microcomputer; |
| Claim: | a break controller responsive to the guard verify signal to generate and send an emulation stop signal to the emulation chip; and |
| Claim: | a supervisor means for controlling the entire system, the supervisor means controlling the guard controller so that the content of the information memory is copied to the guard controller in the supervisor mode before the emulation chip starts to execute the program, stored in the emulation memory, in the emulation mode, the supervisor means selectively either controlling the emulation chip in the supervisor mode or allowing the emulation chip to emulate said program in the emulation mode in such a manner that when the emulation chip emulates said program, stored in the emulation memory, in an emulation mode, if said emulation stop signal is generated, the emulation chip is put into the supervisor mode. |
| Claim: | 2. A microcomputer development system as claimed in claim 1 wherein the emulation chip is assembled on a common emulation board, and the information memory is assembled on a local emulation board distinct from the common emulation board and releasably coupled to the common emulation board. |
| Claim: | 3. A microcomputer development system as claimed in claim 1 further including a local emulation chip provided independently of the emulation chip, said local emulation chip, coupled to the emulation memory in the emulation mode, for emulating a peripheral hardware portion of the target microcomputer, the break controller operating to generate and send the emulation stop signal to the emulation chip and to the local emulation chip when at least one of input/output signals of the local emulation chip satisfies a condition set by the supervisor means; said input/output signals of the local emulation chip including a signal from the emulation memory to said local emulation chip and a signal generated from said local emulation chip in the course of the emulation. |
| Claim: | 4. A microcomputer development system as claimed in claim 3 wherein the emulation chip is assembled on a common emulation board, and the information memory and the local emulation chip are assembled on a local emulation board distinct from the common emulation board and releasably coupled to the common emulation board. |
| Claim: | 5. A microcomputer development system for a family of one-chip microcomputers which are all of a same architecture but differ at least in memory size and in a number of input/output connections, the system comprising |
| Claim: | a common emulation chip having a largest memory size and a largest input/output number from among all of the one-chip microcomputers of said family |
| Claim: | an emulation memory containing a user's program for a target microcomputer, the emulation memory being accessible by the common emulation chip in an emulation mode |
| Claim: | a supervisor means for controlling the entire system |
| Claim: | a control program memory accessible by the supervisor means and by the common emulation chip in a supervisor mode |
| Claim: | a mode selector connecting the common emulation chip to the control program memory in the supervisor mode and to the emulation memory in the emulation mode |
| Claim: | a mode selector controller controlled by the supervisor means to generate and send a mode select signal to the mode selector so as to put it either in the supervisor mode or the emulation mode |
| Claim: | an information memory for storing information indicating resources which can be used by the target microcomputer |
| Claim: | a guard controller, connected to said information memory, for copying a content of the information memory in the supervisor mode before the common emulation chip starts to execute the user's program, stored in the emulation memory, in the emulation mode, the guard controller, in the emulation mode, comparing information written in the guard controller with address information from the common emulation chip so as to generate and send a guard verify signal when the address information indicates access to a resource which cannot be used by the target microcomputer, and |
| Claim: | a break controller, responsive to the guard verify signal, to generate and send an emulation stop signal to the common emulation chip; and wherein |
| Claim: | the supervisor means controls the guard controller such that the content of the information memory is copied to the guard controller in the supervisor mode before the common emulation chip starts to execute the user's program, stored in the emulation memory, in the emulation mode, the supervisor means selectively either controlling the common emulation chip in the supervisor mode or allowing the common emulation chip to emulate said user's program in the emulation mode in such a manner that when the common emulation chip emulates said user's program, stored in the emulation memory, in an emulation mode, the common emulation chip is put into the supervisor mode if said emulation stop signal is generated. |
| Claim: | 6. A microcomputer development system as claimed in claim 5 further including a local emulation chip for emulating peripheral hardware of the target microcomputer, the guard controller operating to generate and send the guard verify signal to the break controller when the local emulation chip accesses a peripheral hardware which is not to be included in the target microcomputer. |
| Claim: | 7. A microcomputer development system as claimed in claim 6, wherein the local emulation chip and the information memory are on a first board which is distinct from a second board, said second board including at least the common emulation chip. |
| Claim: | 8. A microcomputer development system as claimed in claim 7, wherein the first board is releasably connectable to the second board. |
| Claim: | 9. A microcomputer development system as claimed in claim 8, wherein the information memory and the guard controller are controlled by the supervisor means so that a memory area information of the information memory is copied by the guard controller. |
| Claim: | 10. A microcomputer development system as claimed in claim 6, wherein the common emulation chip and the local emulation chip access the emulation memory through the mode selector in the emulation mode. |
| Claim: | 11. A microcomputer development system as claimed in claim 6, wherein the emulation stop signal is outputted to the common emulation chip, the local emulation chip and the mode selector controller, so that the system is put in the supervisor mode. |
| Claim: | 12. A microcomputer development system as claimed in claim 5, wherein the break controller generates the emulation stop signal when the guard verify signal is outputted from the guard controller or when predetermined conditions set by the supervisor means are satisfied. |
| Current U.S. Class: | 364/900; 371/20 |
| Current International Class: | G06F 1130 |
| Patent References Cited: | 4447876 May 1984 Moore 4486827 December 1984 Shima et al. 4633417 December 1986 Wilburn et al. 4638423 January 1987 Ballard 4674089 June 1987 Poret et al. 4691316 September 1987 Phillips 4727512 February 1988 Birkner et al. 4780819 November 1988 Kashiwagi 4788683 November 1988 Hester et al. |
| Primary Examiner: | Shaw, Gareth D. |
| Assistant Examiner: | Napiorkowski, Maria |
| Attorney, Agent or Firm: | Foley & Lardner, Schwartz, Jeffery, Schwaab, Mack, Blumenthal & Evans |
| رقم الانضمام: | edspgr.04847805 |
| قاعدة البيانات: | USPTO Patent Grants |
| الوصف غير متاح. |