التفاصيل البيبلوغرافية
| العنوان: |
Providing Automatic Power Control For A Power Amplifier |
| Document Number: |
20130002357 |
| تاريخ النشر: |
January 3, 2013 |
| Appl. No: |
13/173791 |
| Application Filed: |
June 30, 2011 |
| مستخلص: |
A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level. |
| Inventors: |
Thomsen, Axel (Austin, TX, US); Wang, Zhongda (Sunnyvale, CA, US); Wong, Sai Chu (San Jose, CA, US); Huang, Yunteng (Palo Alto, CA, US) |
| Claim: |
1. An apparatus comprising: a power control circuit to receive a feedback signal from a power amplifier (PA) and to generate a first control signal to control a variable gain amplifier (VGA) based on the feedback signal, wherein the VGA is coupled to an input to the PA, the power control circuit including: a mute circuit to generate a mute signal to be provided to the VGA when the first control signal is less than a first level; and a clamp circuit to clamp a second control signal from exceeding a threshold level, the second control signal used to generate the first control signal. |
| Claim: |
2. The apparatus of claim 1, further comprising an integrator to integrate the feedback signal, an offset signal, and a ramp reference signal to obtain an integrator output corresponding to the second control signal. |
| Claim: |
3. The apparatus of claim 1, further comprising an output stage to provide the first control signal to the VGA, the output stage comprising a comparator to compare a first current output by a first switch device to a first reference current and to provide a difference between the first current and the first reference current as the first control signal. |
| Claim: |
4. The apparatus of claim 3, wherein the mute circuit comprises a second comparator to compare a second current output by a second switch device to a second reference current and to provide a difference between the second current and the second reference current as the mute signal. |
| Claim: |
5. The apparatus of claim 4, wherein the second current is less than the first current. |
| Claim: |
6. The apparatus of claim 4, further comprising a bias circuit to generate a bias signal for the clamp circuit, wherein the bias circuit comprises a third comparator to compare a third current output by a third switch device to a third reference current and to provide a difference between the third current and the third reference current as the bias signal. |
| Claim: |
7. The apparatus of claim 4, wherein the mute circuit is to further provide the mute signal to a gain stage coupled between the VGA and the PA. |
| Claim: |
8. The apparatus of claim 7, wherein the mute signal is to prevent a feed through signal from being output by the VGA or the gain stage when the PA is in an off-key state. |
| Claim: |
9. The apparatus of claim 2, wherein the power control circuit further comprises: a replica circuit to generate a replica voltage, the replica voltage corresponding to the feedback signal when the PA outputs zero current; a converter to convert the replica voltage to a replica current; and a clamp bias circuit to generate a gate signal for the clamp circuit based on a second offset current. |
| Claim: |
10. The apparatus of claim 9, wherein the clamp circuit comprises a switch to clamp the second control signal when the switch is gated by the gate signal. |
| Claim: |
11. A method comprising: receiving a feedback signal from an output of a power amplifier (PA); combining a feedback current generated from the feedback signal with an offset current and a ramp current to obtain a current sum, and providing the current sum to an integrator having an integrator output; providing a control signal to a variable gain amplifier (VGA) and amplifying a radio frequency (RF) signal using the VGA and at least one gain stage coupled between the VGA and the PA when the integrator output is within a first range; and providing a mute signal that prevents a feed through signal from being amplified in at least one of the VGA and the at least one gain stage when the integrator output is within a second range in which the control signal is not provided. |
| Claim: |
12. The method of claim 11, further comprising clamping the integrator output from rising above a threshold level. |
| Claim: |
13. The method of claim 11, further comprising comparing a first current output by a first switch device enabled by the integrator output to a first reference current and providing a difference between the first current and the first reference current as the control signal. |
| Claim: |
14. The method of claim 13, further comprising comparing a second current output by a second switch device enabled by the integrator output to a second reference current and providing a difference between the second current and the second reference current as the mute signal. |
| Claim: |
15. The method of claim 14, wherein in an off-key state, first not providing the control signal, thereafter providing the mute signal, and thereafter preventing the integrator output from departing from the second range. |
| Claim: |
16. The method of claim 11, further comprising providing the mute signal during an off-key state and not providing the mute signal during an on-key state. |
| Claim: |
17. The method of claim 16, wherein the ramp current is zero in the off-key state. |
| Claim: |
18. A system comprising: a processor; a transmitter coupled to the processor and including: a variable gain amplifier (VGA) to receive and amplify a radio frequency (RF) signal; at least one gain stage coupled to an output of the VGA to further amplify the RF signal; a power amplifier (PA) coupled to the at least one gain stage to amplify the RF signal for transmission from the transmitter; and a power control circuit to receive a feedback signal from the PA to control the VGA based on the feedback signal, wherein the power control circuit is to enable the VGA during an on-keying state, and to disable the VGA during an off-keying state, and to further provide a mute signal to the VGA during the off-keying state to prevent a feed through signal from being amplified by the VGA. |
| Claim: |
19. The system of claim 18, wherein the power control circuit further comprises an integrator to generate a gate voltage for an output stage of the power control circuit that outputs a control signal to the VGA and a mute circuit of the power control circuit that provides the mute signal to the VGA. |
| Claim: |
20. The system of claim 19, wherein the power control circuit further comprises a clamp circuit to clamp the gate voltage at a predetermined level in the off-keying state. |
| Current U.S. Class: |
330/279 |
| Current International Class: |
03 |
| رقم الانضمام: |
edspap.20130002357 |
| قاعدة البيانات: |
USPTO Patent Applications |