التفاصيل البيبلوغرافية
| العنوان: |
NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING |
| Document Number: |
20100295102 |
| تاريخ النشر: |
November 25, 2010 |
| Appl. No: |
12/826033 |
| Application Filed: |
June 29, 2010 |
| مستخلص: |
Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described. |
| Inventors: |
SANKIN, Igor (Perrysburg, OH, US); MERRETT, Joseph Neil (Starkville, MS, US) |
| Assignees: |
SEMISOUTH LABORATORIES, INC. (Starkville, MS, US) |
| Claim: |
1-13. (canceled) |
| Claim: |
14. A semiconductor device made by a method comprising: positioning a first mask on a first layer of n-type semiconductor material, wherein the first layer is on a substrate; using the first mask, selectively implanting p-type dopants in the first layer of n-type semiconductor material to form a p-type implanted region adjacent a non-implanted region in the first layer; removing the first mask; epitaxially growing a third layer of n-type semiconductor material on the first layer; epitaxially growing a fourth layer of n-type semiconductor type material on the third layer; positioning a second mask on the fourth layer; selectively etching through the fourth layer to expose underlying third layer through openings in the second mask thereby forming raised features of n-type semiconductor material over the p-type implanted region of the first layer and one or more raised features of n-type semiconductor material over the non-implanted region of the first layer; removing the second mask; positioning a third mask which masks the raised features and the area between the raised features over the p-type implanted region of the first layer and which masks the raised feature over the non-implanted region of the first layer; using the third mask, selectively etching through the third layer to expose p-type implanted and non-implanted regions of the underlying first layer thereby forming first and second raised structures, the first raised structure comprising the raised features over the p-type implanted region of the first layer and the region of the third layer therebetween and the second raised structure comprising the raised feature over the non-implanted region of the first layer, the second raised structure having sidewalls; removing the third mask; forming ohmic contacts on exposed surfaces of the raised features of n-type semiconductor material and on the exposed p-type implanted region of the first layer; and forming Schottky contacts on the third layer between the raised features over the p-type implanted region, on the non-implanted portion of the first layer adjacent the second raised structure and on material of the third layer on the sidewalls of the second raised structure. |
| Claim: |
15. A monolithic integrated circuit comprising a lateral junction field effect transistor and a vertical junction field effect transistor; the lateral junction field effect transistor comprising: a buffer layer of a p-type semiconductor material formed in a portion of a first major surface of a drift layer; a channel layer of an n-type semiconductor material on and non-coextensive with the buffer layer such that a portion of the buffer layer is exposed; discrete source and drain regions of an n-type semiconductor material in spaced relation on the channel layer; a gate region of a p-type semiconductor material formed in the channel layer between the source and drain regions and forming a rectifying junction with the channel layer; ohmic contacts on the source region, the gate region, the drain region and on the exposed portion of the buffer layer; the vertical junction field effect transistor comprising: a channel layer of an n-type semiconductor material on the first major surface of the drift layer laterally spaced from the buffer layer; one or more discrete source regions of an n-type semiconductor material in spaced relation on the channel layer; a gate region of a p-type semiconductor material formed in the channel layer adjacent the one or more source regions and forming a rectifying junction with the channel layer; and ohmic contacts on the gate and source regions; wherein the drift layer is on a first major surface of a substrate; and wherein an electrical contact is on a second major surface of the substrate opposite the first major surface of the substrate. |
| Claim: |
16. The integrated circuit of claim 15, wherein a drain layer of an n-type semiconductor material is between the drift layer and the first major surface of the substrate. |
| Claim: |
17. The integrated circuit of claim 15, further comprising: a first electrical connection between the source contact of the lateral channel JFET and the gate contact of the vertical channel JFET; a second electrical connection between the gate and buffer layer contacts of the lateral channel JFET; and a third electrical connection between the drain contact of the lateral channel JFET and the source contact of the vertical channel JFET. |
| Claim: |
18. The integrated circuit of claim 15, further comprising one or more rings of p-type semiconductor material formed in the drift layer and circumscribing the lateral junction field effect transistor. |
| Claim: |
19. The integrated circuit of claim 15, further comprising one or more rings of p-type semiconductor material formed in the drift layer and circumscribing the vertical junction field effect transistor. |
| Claim: |
20. A monolithic integrated circuit comprising a lateral junction field effect transistor and a vertical junction field effect transistor; the lateral junction field effect transistor comprising: a buffer layer of a p-type semiconductor material formed in a portion of a first major surface of a drift layer; a channel layer of an n-type semiconductor material on and non-coextensive with the buffer layer such that a portion of the buffer layer is exposed; discrete source and drain regions each of an n-type semiconductor material in spaced relation on the channel layer; a metal layer on the channel layer between the source and drain regions forming a metal-semiconductor rectifying junction with the channel layer; ohmic contacts on the source region, the drain region and on the exposed portion of the buffer layer; the vertical junction field effect transistor comprising: one or more raised regions on the first major surface of the drift layer laterally spaced from the buffer layer each comprising a channel region of an n-type semiconductor material on the first major surface of the drift layer and spaced from the buffer layer of the lateral junction field effect transistor and a source region of an n-type semiconductor material on the channel region; a metal layer on the drift layer adjacent to the one or more raised regions forming a metal-semiconductor rectifying junction with the drift layer and the channel region(s); and an ohmic contact on the source region; wherein the drift layer is on a first major surface of a substrate; and wherein an electrical contact is on a second major surface of the substrate opposite the first major surface of the substrate. |
| Claim: |
21. The integrated circuit of claim 20, wherein a drain layer of an n-type semiconductor material is between the drift layer and the first major surface of the substrate. |
| Claim: |
22. The integrated circuit of claim 20, further comprising: a first electrical connection between the source contact of the lateral junction field effect transistor and the metal layer of the vertical junction field effect transistor; a second electrical connection between the metal layer and buffer contacts of the lateral junction field effect transistor; and a third electrical connection between the drain contact of the lateral junction field effect transistor and the source contact of the vertical junction field effect transistor. |
| Claim: |
23. The integrated circuit of claim 20, further comprising one or more rings of p-type semiconductor material formed in the drift layer and circumscribing the lateral channel junction field effect transistor. |
| Claim: |
24. The integrated circuit of claim 20, further comprising one or more rings of p-type semiconductor material formed in the drift layer and circumscribing the vertical channel junction field effect transistor. |
| Current U.S. Class: |
257/265 |
| Current International Class: |
01; 01 |
| رقم الانضمام: |
edspap.20100295102 |
| قاعدة البيانات: |
USPTO Patent Applications |