التفاصيل البيبلوغرافية
| العنوان: |
NONVOLATILE FLASH MEMORY DEVICE AND METHOD FOR PRODUCING THE SAME |
| Document Number: |
20090189215 |
| تاريخ النشر: |
July 30, 2009 |
| Appl. No: |
11/912006 |
| Application Filed: |
April 20, 2005 |
| مستخلص: |
A method of producing metallic nanocrystals (107) embedded in high-k dielectric material as well as a nonvolatile flash memory device (100) comprising a discrete charge carrier storage layer, the discrete charge carrier storage layer comprising metallic nanocrystals (107) embedded in high-k dielectric material. In the method described in this invention, firstly an ultra-thin metal film is deposited over a first (105) and a second (106) dielectric layer including high-k dielectric material provided on a substrate (101). Then, the ultra-thin metal film is annealed for forming the metallic nanocrystals (107) on the second dielectric layer (106). Finally, the second dielectric layer (106) and the metallic nanocrystals (107) are covered with a third dielectric layer (108) of high-k dielectric material for forming metallic nanocrystals (107) embedded in high-k dielectric material. The first (105), second (106) and third (108) dielectric layers together with the embedded metallic nanocrystals (107) as the discrete charge carrier storage layer form the nonvolatile flash memory device (100). |
| Inventors: |
Samanta, Santanu Kumar (Singapore, SG); Yoo, Won Jong (Gyeonggi-do, KR) |
| Assignees: |
NATIONAL UNIVERSITY OF SINGAPORE (Singapore, SG) |
| Claim: |
1-49. (canceled) |
| Claim: |
50. A nonvolatile flash memory device comprising a discrete charge carrier storage layer, the discrete charge carrier storage layer comprising metallic nanocrystals embedded in high-k dielectric material, wherein the discrete charge carrier storage layer comprises a layer stack successively having a first dielectric layer, a second dielectric layer and a third dielectric layer, each of the first, second and third dielectric layers comprising high-k dielectric material, and wherein the metallic nanocrystals are embedded between the second dielectric layer and the third dielectric layer, and the second dielectric layer is a diffusion barrier layer for the metallic nanocrystals. |
| Claim: |
51. The nonvolatile flash memory device as claimed in claim 50, wherein the first and third dielectric layers comprise a hafnium oxide-based or zirconium oxide-based high-k dielectric material. |
| Claim: |
52. The nonvolatile flash memory device as claimed in claim 50, wherein the first dielectric layer comprises a thickness between about 3 nm and about 7 nm. |
| Claim: |
53. The nonvolatile flash memory device as claimed in claim 50, wherein the first dielectric layer comprises a thickness of about 5 nm. |
| Claim: |
54. The nonvolatile flash memory device as claimed in claim 50, wherein the second dielectric layer comprises a thickness between about 0.5 nm and about 1.5 nm. |
| Claim: |
55. The nonvolatile flash memory device as claimed in claim 54, wherein the second 5dielectric layer comprises a thickness of about 1 nm. |
| Claim: |
56. The nonvolatile flash memory device as claimed in claim 50, wherein the third dielectric layer comprises a thickness between about 8 nm and about 10 nm. |
| Claim: |
57. The nonvolatile flash memory device as claimed in claim 50, wherein the discrete charge carrier storage layer is arranged above a substrate. |
| Claim: |
58. The nonvolatile flash memory device as claimed in claim 57, wherein the substrate comprises silicon. |
| Claim: |
59. The nonvolatile flash memory device as claimed in claim 57, wherein a control gate layer is located above the discrete charge carrier storage layer, wherein a channel region is located between the discrete charge carrier storage layer and the substrate, and wherein source and drain regions are located on opposite sides of the channel region on and/or in the substrate. |
| Claim: |
60. The nonvolatile flash memory device as claimed in claim 50, wherein the first and third dielectric layers comprise a first high-k dielectric material selected from the group consisting of hafnium aluminate (HfAlO), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), and zirconium oxide (ZrO2). |
| Claim: |
61. The nonvolatile flash memory device as claimed in claim 50, wherein the second dielectric layer comprises a second high-k dielectric material selected from the group consisting of aluminum (III) oxide (Al2O3), silicon (IV) nitride (Si3N4), and titanium (IV) oxide (TiO2). |
| Claim: |
62. The nonvolatile flash memory device as claimed in claim 50, wherein the metallic nanocrystals comprise a material selected from the group consisting of cobalt, gold, nickel, palladium, platinum, silver, tungsten, and titanium nitride. |
| Claim: |
63. The nonvolatile flash memory device as claimed in claim 50, wherein the metallic nanocrystals comprise a maximum dimension of less than or equal to 10 nm. |
| Claim: |
64. The nonvolatile flash memory device as claimed in claim 63, wherein the metallic nanocrystals comprise a maximum dimension of between about 5 nm and about 7 nm. |
| Claim: |
65. The nonvolatile flash memory device as claimed in claim 64, wherein the metallic nanocrystals comprise a maximum dimension of equal to 5 nm. |
| Claim: |
66. The nonvolatile flash memory device as claimed in claim 50, wherein the metallic nanocrystals are distributed in a self-assembled manner. |
| Claim: |
67. The nonvolatile flash memory device as claimed in claim 50, wherein the metallic nanocrystals are distributed substantially two-dimensionally in the discrete charge carrier storage layer. |
| Claim: |
68. The nonvolatile flash memory device as claimed in claim 50, wherein the metallic nanocrystals are distributed in the discrete charge carrier storage layer with a density of about 5×1011/cm2. |
| Claim: |
69. A method of producing metallic nanocrystals embedded in high-k dielectric material, comprising: a) providing a substrate covered with a first dielectric layer of a first high-k dielectric material; b) depositing a second dielectric layer of a second high-k dielectric material over the first dielectric layer; c) depositing an ultra-thin metal film over the second dielectric layer; d) annealing the ultra-thin metal film, thereby forming metallic nanocrystals on the second dielectric layer; and e) covering the second dielectric layer and the metallic nanocrystals with a third dielectric layer of the first high-k dielectric material such that the metallic nanocrystals are embedded between the second dielectric layer and the third dielectric layer, thereby forming metallic nanocrystals embedded in high-k dielectric material, wherein the second dielectric layer is a diffusion barrier layer for the metallic nanocrystals. |
| Claim: |
70. The method as claimed in claim 69, wherein step d) is carried out in a substantially inert ambient. |
| Claim: |
71. The method as claimed in claim 69, wherein step d) is carried out in an ambient substantially comprising nitrogen. |
| Claim: |
72. The method as claimed in claim 69, wherein step d) is carried out at a temperature between about 500° C. and about 1,000° C. |
| Claim: |
73. The method as claimed in claim 69, wherein step d) is carried out at a duration of between 20 sec and 2 min. |
| Claim: |
74. The method as claimed in claim 69, wherein the first high-k dielectric material used in steps a) and e) is a hafnium oxide-based or zirconium oxide-based high-k dielectric material. |
| Claim: |
75. The method as claimed in claim 74, wherein the first high-k dielectric material used in steps a) and e) is selected from the group consisting of hafnium aluminate (HfAlO), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), and zirconium oxide (ZrO2). |
| Claim: |
76. The method as claimed in claim 69, wherein the second high-k dielectric material used in step b) is selected from the group consisting of aluminum (III) oxide (Al2O3), silicon (IV) nitride (Si3N4), and titanium (IV) oxide (TiO2). |
| Claim: |
77. The method as claimed in claim 69, wherein in step c) a metallic material is used, which metallic material is selected from the group consisting of cobalt, gold, nickel, palladium, platinum, silver, tungsten, and titanium nitride. |
| Claim: |
78. The method as claimed in claim 69, wherein in step d) metallic nanocrystals are formed, the maximum dimension of which is less than or equal to about 10 nm. |
| Claim: |
79. The method as claimed in claim 78, wherein in step d) metallic nanocrystals are formed, the maximum dimension of which is between about 5 nm and about 7 nm. |
| Claim: |
80. The method as claimed in claim 69, wherein in step d) metallic nanocrystals are formed, which are distributed in a self-assembled manner. |
| Claim: |
81. The method as claimed in claim 69, wherein in step d) metallic nanocrystals are formed, which are distributed substantially two-dimensionally on the second dielectric layer. |
| Claim: |
82. The method as claimed in claim 69, wherein in step d) metallic nanocrystals are formed, which are distributed on the second dielectric layer with a density of about 5×1011/cm2. |
| Claim: |
83. The method as claimed in claim 69, wherein the first dielectric layer in step a) is provided with a thickness between about 3 nm and about 7 nm. |
| Claim: |
84. The method as claimed in claim 69, wherein the first dielectric layer is provided in step a) by atomic layer deposition of the first high-k dielectric material onto the substrate. |
| Claim: |
85. The method as claimed in claim 69, wherein the second dielectric layer is deposited in step b) with a thickness between about 0.5 nm and about 1.5 nm. |
| Claim: |
86. The method as claimed in claim 69, wherein the second dielectric layer is deposited in step b) by atomic layer deposition of the second high-k dielectric material onto the first dielectric layer. |
| Claim: |
87. The method as claimed in claim 69, wherein the ultra-thin metal layer is deposited in step c) with a thickness of between about 1 nm and about 5 nm. |
| Claim: |
88. The method as claimed in claim 69, wherein the ultra-thin metal layer is deposited in step c) by sputtering metal onto the second dielectric layer. |
| Claim: |
89. The method as claimed in claim 88, wherein in step c) the metal is sputtered for a sputtering period of between about 10 sec and about 60 sec. |
| Claim: |
90. The method as claimed in claim 88, wherein in step c) the metal is sputtered for a sputtering period of about 30 sec. |
| Claim: |
91. The method as claimed in claim 69, wherein the third dielectric layer is deposited in step e) with a thickness of between about 8 nm and about 10 nm. |
| Claim: |
92. The method as claimed in claim 69, wherein the third dielectric layer is deposited in step e) by atomic layer deposition of the first high-k dielectric material onto the second dielectric layer and the metallic nanocrystals. |
| Claim: |
93. The method as claimed in claim 69, wherein the first dielectric layer in step a) is provided on a substrate comprising silicon. |
| Current U.S. Class: |
257/325 |
| Current International Class: |
01; 01 |
| رقم الانضمام: |
edspap.20090189215 |
| قاعدة البيانات: |
USPTO Patent Applications |