التفاصيل البيبلوغرافية
| العنوان: |
Structure for reducing stress for vias and fabricating method thereof |
| Document Number: |
20090156001 |
| تاريخ النشر: |
June 18, 2009 |
| Appl. No: |
12/379223 |
| Application Filed: |
February 17, 2009 |
| مستخلص: |
A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block. |
| Inventors: |
Hsu, Yung-Yu (Hsinchu, TW); Feng, Rong-Chang (Hsinchu, TW); Tain, Ra-Min (Hsinchu, TW); Liau, Shyi-Ching (Hsinchu, TW); Lin, Ji-cheng (Hsinchu, TW); Yu, Shan-Pu (Hsinchu, TW); Chen, Shou-Lung (Hsinchu, TW); Cheng, Chih-Yuan (Hsinchu, TW) |
| Claim: |
1.-7. (canceled) |
| Claim: |
8. A fabricating method of a structure for reducing stress for vias, comprising the following steps: providing at least a first conductor; forming at least a stress block at the position corresponding to the first conductor, wherein the stress block is in a lattice structure; forming an insulation layer to cover the first conductor, and the stress block; forming at least a through hole passing through the interior of the stress block in the insulation layer corresponding to the first conductor; and forming at least a second conductor on the insulation layer, and forming a via in each through hole, to connect the first conductor and the second conductor by the via. |
| Claim: |
9. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, further comprising the step of providing a substrate, wherein the first conductor is disposed on the substrate. |
| Claim: |
10. The fabricating method of a structure for reducing stress for vias as claimed in claim 9, wherein the substrate is selected from the group consisting of an organic substrate, a semiconductor substrate, and a wafer. |
| Claim: |
11. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the step of providing at least a first conductor includes the step of providing another insulation layer, wherein the first conductor is disposed on the other insulation layer. |
| Claim: |
12. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the lattice structure includes at least a frame, and each frame is provided with at least one of the vias passing therethrough. |
| Claim: |
13. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the CTE of the stress block is less than the CTE of the insulation layer. |
| Claim: |
14. The fabricating method of a structure for reducing stress for vias as claimed in claim 13, wherein the material parameter of the stress block is approximate to the material parameter of the second conductor. |
| Claim: |
15. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the method of forming the stress block is selected from the group consisting of mask electroplating, lamination, bonding, conjunction, and adhesion. |
| Claim: |
16. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the first conductor is selected from the group consisting of a conductive line and a microelectronic die, and the second conductor is also selected from the group consisting of a conductive line and a microelectronic die. |
| Claim: |
17. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the method of forming the through hole is selected from the group consisting of mechanical hole boring, chemical etching, and laser hole drilling. |
| Claim: |
18. The fabricating method of a structure for reducing stress for vias as claimed in claim 8, wherein the type of the via is selected from the group consisting of a wire form, a through form, and a blind via form. |
| Current U.S. Class: |
438/667 |
| Current International Class: |
01 |
| رقم الانضمام: |
edspap.20090156001 |
| قاعدة البيانات: |
USPTO Patent Applications |