التفاصيل البيبلوغرافية
| العنوان: |
Data reception apparatus and microcomputer having the same |
| Document Number: |
20090096504 |
| تاريخ النشر: |
April 16, 2009 |
| Appl. No: |
12/285581 |
| Application Filed: |
October 09, 2008 |
| مستخلص: |
A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value. |
| Inventors: |
Matsuo, Kazushi (Nukata-gun, JP); Matsuoka, Toshihiko (Nukata-gun, JP); Ishihara, Hideaki (Okazaki-city, JP) |
| Assignees: |
DENSO CORPORATION (Kariya-city, JP) |
| Claim: |
1. A data reception apparatus comprising: an oscillation circuit including a CR oscillator, wherein the CR oscillator outputs an oscillation signal, the oscillation circuit multiplies or divides the oscillation signal based on a cycle setting value, and the oscillation circuit outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector that detects a temperature around the CR oscillator; a memory that stores the cycle setting value in association with the temperature; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value corresponding to the temperature based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value in association with the temperature in the memory. |
| Claim: |
2. The data reception apparatus of claim 1, wherein the correction element calculates a difference between the corrected cycle setting value and the cycle setting value in association with the temperature, and adds the difference to the cycle setting value corresponding to each temperature in the memory. |
| Claim: |
3. The data reception apparatus of claim 1, wherein the correction element calculates a difference between the corrected cycle setting value and the cycle setting value in association with the temperature, and adds a value to the cycle setting value corresponding to each temperature in the memory, and wherein the value is obtained by weighting the difference with the temperature. |
| Claim: |
4. The data reception apparatus of claim 1, wherein the correction element rewrites the cycle setting value with the corrected cycle setting value only when the corrected cycle setting value is successively matched for a predetermined number of times. |
| Claim: |
5. The data reception apparatus of claim 4, wherein the correction element rewrites the cycle setting value with the corrected cycle setting value when the corrected cycle setting value straight increases or decreases for the predetermined times and even when the corrected cycle setting value is not successively matched for the predetermined number of times. |
| Claim: |
6. The data reception apparatus of claim 1, wherein the measurement element measures the unit bit length when the measurement element detects a predetermined synchronization signal contained in the data signal received by the receiver. |
| Claim: |
7. The data reception apparatus of claim 1, wherein the correction element calculates a difference between the corrected cycle setting value and the cycle setting value, and wherein the correction element corrects and rewrites the cycle setting value when the difference is equal to or smaller than a predetermined threshold value. |
| Claim: |
8. A data reception apparatus comprising: an oscillation circuit including a CR oscillator, wherein the CR oscillator outputs an oscillation signal, the oscillation circuit multiplies or divides the oscillation signal based on a cycle setting value, and the oscillation circuit outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector that detects a temperature around the CR oscillator; a voltage detector that detects a power supply voltage supplied to the CR oscillator; a memory that stores the cycle setting value in association with the temperature and the power supply voltage; a clock cycle setting element that reads the cycle setting value corresponding to the temperature and the power supply voltage from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value corresponding to the temperature and the power supply voltage based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value in association with the temperature and the power supply voltage in the memory. |
| Claim: |
9. The data reception apparatus of claim 8, wherein the correction element calculates a difference between the corrected cycle setting value and the cycle setting value in association with the temperature and the power supply voltage, and adds the difference to the cycle setting value corresponding to each temperature and each power supply voltage in the memory. |
| Claim: |
10. The data reception apparatus of claim 8, wherein the correction element calculates a difference between the corrected cycle setting value and the cycle setting value in association with the temperature and the power supply voltage, and adds a value to the cycle setting value corresponding to each temperature and each power supply voltage in the memory, and wherein the value is obtained by weighting the difference with the temperature and the power supply voltage. |
| Claim: |
11. The data reception apparatus of claim 8, wherein the correction element rewrites the cycle setting value with the corrected cycle setting value only when the corrected cycle setting value is successively matched for a predetermined number of times. |
| Claim: |
12. The data reception apparatus of claim 11, wherein the correction element rewrites the cycle setting value with the corrected cycle setting value when the corrected cycle setting value straight increases or decreases for the predetermined times and even when the corrected cycle setting value is not successively matched for the predetermined number of times. |
| Claim: |
13. The data reception apparatus of claim 8, wherein the measurement element measures the unit bit length when the measurement element detects a predetermined synchronization signal contained in the data signal received by the receiver. |
| Claim: |
14. The data reception apparatus of claim 8, wherein the correction element calculates a difference between the corrected cycle setting value and the cycle setting value, and wherein the correction element corrects and rewrites the cycle setting value when the difference is equal to or smaller than a predetermined threshold value. |
| Claim: |
15. A microcomputer comprising: a data reception apparatus of claim 1, wherein the clock signal provides a system clock signal. |
| Claim: |
16. The microcomputer of claim 15 further comprising: a data transmission apparatus for transmitting the data signal; and a higher order computer, wherein the data transmission apparatus transmits the count value of the clock signal and the cycle setting value to the higher order computer instead of correcting the cycle setting value by the correction element, wherein the higher-order computer corrects the cycle setting value based on the count value of the clock signal and the reference count value of the reference cycle corresponding to the unit bit length, wherein the higher-order computer outputs the corrected cycle setting value to the oscillation circuit so that the corrected cycle setting value is set in the oscillation circuit, and wherein the higher-order computer rewrites the cycle setting value with the corrected cycle setting value in association with the temperature in the memory. |
| Current U.S. Class: |
327/513 |
| Current International Class: |
03 |
| رقم الانضمام: |
edspap.20090096504 |
| قاعدة البيانات: |
USPTO Patent Applications |