التفاصيل البيبلوغرافية
| العنوان: |
INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR ARRANGEMENT |
| Document Number: |
20080179669 |
| تاريخ النشر: |
July 31, 2008 |
| Appl. No: |
11/680320 |
| Application Filed: |
February 28, 2007 |
| مستخلص: |
An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer. |
| Inventors: |
Detzel, Thomas (Villach, AT); Maier, Hubert (Villach, AT); Schreiber, Kai-Alexander (Villach, AT); Woehlert, Stefan (Villach, AT); Hoeckele, Uwe (Regensburg, DE) |
| Assignees: |
INFINEON TECHNOLOGIES AUSTRIA AG (Villach, AT) |
| Claim: |
1. An integrated circuit having a semiconductor arrangement comprising: a first interconnect layer; an insulating layer having at least one cutout; a second interconnect layer; and an SiON layer between the first interconnect layer and the second interconnect layer. |
| Claim: |
2. The integrated circuit of claim 1, comprising: wherein the SiON layer has an optical refractive index of approximately 1.7 |
| Claim: |
3. The integrated circuit of claim 1, comprising wherein the filling layer constitutes an HDP oxide layer |
| Claim: |
4. The integrated circuit of claim 1, comprising wherein an insulating covering layer is formed between the SiON layer and the second interconnect layer. |
| Claim: |
5. The integrated circuit of claim 4, comprising wherein the covering layer has a layer thickness of 300 nm to 800 nm. |
| Claim: |
6. The integrated circuit of claim 4, comprising wherein the covering layer includes SiO or SiC. |
| Claim: |
7. A semiconductor arrangement, comprising: a carrier substrate; a first interconnect layer, formed on the carrier substrate and having at least one cutout; an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout; an SiON layer, formed on the filling layer; and a second interconnect layer, formed over the SiON layer. |
| Claim: |
8. The semiconductor arrangement of claim 7, comprising wherein the SiON layer has a layer thickness of 0.2 μm to 1 μm. |
| Claim: |
9. The semiconductor arrangement of claim 7, comprising wherein the SiON layer has an optical refractive index of approximately 1.7. |
| Claim: |
10. The semiconductor arrangement of claim 7, comprising wherein the filling layer has a layer thickness corresponding approximately to a layer thickness of the first interconnect layer. |
| Claim: |
11. The semiconductor arrangement of claim 7, comprising wherein the filling layer has a layer thickness 0.8 μm to 1.5 μm. |
| Claim: |
12. The semiconductor arrangement of claim 7, comprising wherein the filling layer constitutes an HDP oxide layer. |
| Claim: |
13. The semiconductor arrangement of claim 7, comprising wherein an insulating covering layer is furthermore formed between the SiON layer and the second interconnect layer. |
| Claim: |
14. The semiconductor arrangement of claim 13, comprising wherein the covering layer has a layer thickness of 300 nm to 800 nm. |
| Claim: |
15. The semiconductor arrangement of claim 13, comprising wherein the covering layer has SiwOxNyHz or SiOxCyHz. |
| Claim: |
16. The semiconductor arrangement of claim 7, comprising wherein the first interconnect layer has Al, Cu, Ni and/or W. |
| Claim: |
17. The semiconductor arrangement of claim 7, comprising wherein the second interconnect layer has Cu, Ni, NiPd and/or NiP. |
| Claim: |
18. A power semiconductor component comprising: a logic transistor region and a power transistor region, formed in a common semiconductor substrate, wherein an insulating carrier layer is formed at least partly at the surface of the semiconductor substrate, on which carrier layer is formed a first interconnect layer having cutouts at least in the logic transistor region; an insulating filling layer is formed on the first interconnect layer and on the carrier layer, which fills the cutouts; an SiON layer is formed on the filling layer; and a second interconnect layer is formed over the SiON layer. |
| Claim: |
19. The power semiconductor component of claim 18, comprising wherein the SiON layer has a layer thickness of 0.2 μm to 1 μm. |
| Claim: |
20. The power semiconductor component of claim 18, comprising wherein the SiON layer has an optical refractive index of approximately 1.7. |
| Claim: |
21. The power semiconductor component of claim 18, comprising wherein the filling layer constitutes an HDP oxide layer. |
| Claim: |
22. The power semiconductor component of claim 18, comprising wherein an insulating covering layer is furthermore formed between the SiON layer and the second interconnect layer. |
| Claim: |
23. The power semiconductor component of claim 18, comprising wherein the power transistor region is separated from the logic transistor region at the surface of the semiconductor substrate by a field plate. |
| Claim: |
24. A DMOS power semiconductor component, comprising: a logic transistor region and a DMOS power transistor region having a multiplicity of trenches filled with a gate dielectric and a gate layer formed thereon, wherein the regions are formed in a common semiconductor substrate; an insulating carrier layer formed at least partly at the surface of the semiconductor substrate, on which carrier layer is formed a first interconnect layer having cutouts at least in the logic transistor region; an insulating filling layer formed on the first interconnect layer and on the carrier layer, which fills the cutouts; an SiON layer formed on the filling layer; an insulating covering layer formed on the SiON layer; and a second interconnect layer formed on the covering layer. |
| Claim: |
25. The DMOS power semiconductor component of claim 24, comprising wherein the SiON layer has a layer thickness of 0.2 μm to 1 μm. |
| Claim: |
26. The DMOS power semiconductor component of claim 24, comprising wherein the SiON layer has an optical refractive index of approximately 1.7. |
| Claim: |
27. The DMOS power semiconductor component of claim 24, comprising wherein the filling layer constitutes an HDP oxide layer. |
| Claim: |
28. The DMOS power semiconductor component of claim 24, comprising wherein the covering layer constitutes a TEOS- or SiH4-based oxide layer having a layer thickness of 300 nm to 800 nm, in particular 600 nm. |
| Claim: |
29. The DMOS power semiconductor component of claim 24, comprising wherein the first and/or second interconnect layer has Al. |
| Claim: |
30. A method for producing a semiconductor arrangement comprising: forming a carrier substrate; forming a first interconnect layer on the carrier substrate; patterning the first interconnect layer to produce at least one cutout; forming an insulating filling layer on the patterned interconnect layer and the carrier substrate; forming an SiON layer on the insulating filling layer; and forming a second interconnect layer over the SiON layer. |
| Claim: |
31. The method of claim 30, comprising carrying out an HDP deposition method for producing an HDP oxide layer. |
| Claim: |
32. The method of claim 30, comprising forming, the SiON layer with a layer thickness of 0.2 μm to 1 μm. |
| Claim: |
33. The method of claim 30, comprising using SiH4, NH3, N2O and N2 as precursor gases in). |
| Claim: |
34. The method of claim 30, comprising carrying out forming the insulating layer and forming the SiON layer in an identical plasma reactor chamber. |
| Claim: |
35. A method of claim 30, comprising carrying out a further process for forming an insulating covering layer on the SiON layer. |
| Claim: |
36. The method of claim 35, comprising producing a TEOS-or SiH4-based oxide layer during the formation of the covering layer. |
| Current U.S. Class: |
257/337 |
| Current International Class: |
01; 01; 01 |
| رقم الانضمام: |
edspap.20080179669 |
| قاعدة البيانات: |
USPTO Patent Applications |