التفاصيل البيبلوغرافية
| العنوان: |
High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage |
| Document Number: |
20060113627 |
| تاريخ النشر: |
June 1, 2006 |
| Appl. No: |
10/999508 |
| Application Filed: |
November 29, 2004 |
| مستخلص: |
A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes. |
| Inventors: |
Chen, Chung-I (Hsinchu City, TW); Kuan, Hsin (Hsinchu, TW); Chen, Zhi-Cheng (Hsinchu City, TW); Yeh, Rann-Shyan (Hsin-Chu City, TW); Chang, Chi-Hsuen (Hsinchu City, TW); Liu, Jun Xiu (Hsinchu, TW); Sung, Tzu-Chiang (Jhubei City, TW); Liu, Chia-Wei (Huatan Township, TW); Chang, Jieh-Ting (Nantou City, TW) |
| Claim: |
1. A semiconductor device, comprising: a gate structure overlying a high-voltage device region of a semiconductor substrate; at least one diffusion region formed in said high-voltage region of said semiconductor substrate and laterally adjacent to the sidewall of said gate structure; an etch stop layer overlying said gate structure and said at least one diffusion region, wherein said etch stop layer has a resistivity greater than 10 ohm-cm; and an interlayer dielectric layer overlying said etch stop layer and having at least one contact hole that penetrates said interlayer dielectric layer and said etch stop layer. |
| Claim: |
2. The semiconductor device of claim 1, wherein said etch stop layer is selected from any dielectric material other than a silicon oxynitride material that has a silicon molar percentage greater than about 55%. |
| Claim: |
3. The semiconductor device of claim 1, wherein said etch stop layer comprises a silicon nitride layer. |
| Claim: |
4. The semiconductor device of claim 1, wherein said etch stop layer comprises a silicon oxide layer and a silicon nitride layer. |
| Claim: |
5. The semiconductor device of claim 1, wherein said etch stop layer comprises a silicon oxynitride layer that has a silicon molar percentage less than about 55%. |
| Claim: |
6. The semiconductor device of claim 1, further comprising a metal silicide layer overlying said at least one diffusion region, wherein said at least one contact hole penetrates said interlayer dielectric layer and said etch stop layer to expose said metal silicide layer. |
| Claim: |
7. The semiconductor device of claim 1, further comprising two isolation regions formed in said semiconductor substrate to define said high-voltage device region. |
| Claim: |
8. The semiconductor device of claim 1, wherein said gate structure comprises: a gate dielectric layer overlying said semiconductor substrate; and a gate electrode layer overlying said gate dielectric layer. |
| Claim: |
9. The semiconductor device of claim 8, wherein said gate structure comprises: a dielectric spacer formed on the sidewall of said gate dielectric layer and said gate electrode layer; and wherein said diffusion region is substantially aligned to an exterior sidewall of said dielectric spacer. |
| Claim: |
10. The semiconductor device of claim 1, wherein said at least one contact hole is filled with a conductive material that is electrically connected to said at least one diffusion region. |
| Claim: |
11. The semiconductor device of claim 1, wherein said semiconductor device is a high-voltage transistor operating at a power supply voltage greater than 5V. |
| Claim: |
12. A high-voltage device process, comprising: providing a semiconductor substrate having a high-voltage device region; forming a gate structure overlying said high-voltage device region of said semiconductor substrate; forming at least one diffusion region in said high-voltage device region of said semiconductor substrate, wherein said at least one diffusion region is laterally adjacent to the sidewall of said gate structure; forming an etch stop layer overlying said gate structure and said at least one diffusion region, wherein said etch stop layer has a resistivity greater than 10 ohm-cm; forming an interlayer dielectric layer overlying said etch stop layer; and forming at least one contact hole penetrating said interlayer dielectric layer and said etch stop layer. |
| Claim: |
13. The high-voltage device process of claim 12, wherein said etch stop layer is selected from any dielectric material other than a silicon oxynitride material that has a silicon molar percentage greater than about 55%. |
| Claim: |
14. The high-voltage device process of claim 12, wherein said etch stop layer comprises a silicon nitride layer. |
| Claim: |
15. The high-voltage device process of claim 12, wherein said etch stop layer comprises a silicon oxide layer and a silicon nitride layer. |
| Claim: |
16. The high-voltage device process of claim 12, wherein said etch stop layer comprises a silicon oxynitride layer that has a silicon molar percentage less than about 55%. |
| Claim: |
17. The high-voltage device process of claim 12, further comprising forming a metal silicide layer overlying said at least one diffusion region before forming said etch stop layer. |
| Claim: |
18. The high-voltage device process of claim 17, wherein said at least one contact hole penetrates said interlayer dielectric layer and said etch stop layer to expose said at least one diffusion region. |
| Claim: |
19. The high-voltage device process of claim 12, further comprising forming two isolation regions in said semiconductor substrate to define said high-voltage device region. |
| Claim: |
20. The high-voltage device process of claim 12, further comprising filling said at least one contact hole with a conductive material that electrically connects to said at least one diffusion region. |
| Current U.S. Class: |
257500/000 |
| Current International Class: |
01 |
| رقم الانضمام: |
edspap.20060113627 |
| قاعدة البيانات: |
USPTO Patent Applications |