التفاصيل البيبلوغرافية
| العنوان: |
1T1R resistive memory array with chained structure |
| Document Number: |
20050248978 |
| تاريخ النشر: |
November 10, 2005 |
| Appl. No: |
11/121145 |
| Application Filed: |
May 03, 2005 |
| مستخلص: |
A 1T1R resistive memory array configured as chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such a configuration is non-volatile and provides for each of the memory cells to be randomly accessed. |
| Inventors: |
Chen, Zheng (Colorado Springs, CO, US); Paz de Araujo, Carlos A. (Colorado springs, CO, US); McMillan, Larry D. (Colorado Springs, CO, US) |
| Assignees: |
Symetrix Corporation (Colorado Springs, CO, US), Matsushita Electric Industrial Co., Ltd. (Kadoma-shi, JP) |
| Claim: |
1. An electronic memory comprising a plurality of memory cells, each memory cell including: a switch; a resistive memory element connected in parallel with said switch, said resistive memory element capable of existing in one of a plurality of resistive states, each resistive state representing a different data state; and a memory write and read circuit selectably coupled to said resistive memory element and capable of writing a data state to said resistive memory element and reading the data state. |
| Claim: |
2. The electronic memory according to claim 1, wherein said switch is a transistor. |
| Claim: |
3. The electronic memory according to claim 1, wherein said plurality of memory cells are arranged in a row/column configuration, each row/column configuration including a plurality of said resistive memory elements connected in series and a plurality of said switches connected in series, each of said switches associated with one of said resistive memory elements. |
| Claim: |
4. The electronic memory according to claim 3, further comprising a source of a programming voltage and a row/column selection transistor connected between said source of the programming voltage and said row/column of memory cells. |
| Claim: |
5. The electronic memory according to claim 3, further comprising a sense amplifier and a row/column sense transistor connected between said sense amplifier and said row/column of memory cells. |
| Claim: |
6. The electronic memory according to claim 1, wherein said resistive memory element includes a material selected from the group consisting of colossal magnetoresistance (CMR) materials and high temperature superconductivity (HTSC) materials. |
| Claim: |
7. The electronic memory according to claim 1, wherein said resistive memory element is composed of Pr0.7Ca0.3MnO3. |
| Claim: |
8. The electronic memory according to claim 1, wherein each of said memory cells has a maximum size of 4 F2. |
| Claim: |
9. A method of writing to an electronic memory including a plurality of memory cells, each memory cell being composed of a resistive memory element, said method comprising: randomly accessing one of the memory cells; and writing data to the randomly accessed memory cell without altering data of any other memory cell. |
| Claim: |
10. The method according to claim 9, wherein said writing includes applying a positive voltage pulse to the randomly accessed memory cell to increase resistance of the memory element of the memory cell. |
| Claim: |
11. The method according to claim 10, wherein said writing includes applying a voltage pulse having reverse polarity from the positive voltage pulse to the randomly accessed memory cell to decrease resistance of the memory element of the memory cell. |
| Claim: |
12. The method according to claim 9, wherein said writing includes increasing and decreasing resistance of the memory element of a memory cell by applying a first voltage level for a first pulse width and a second voltage level for a second pulse width, respectively. |
| Claim: |
13. The method according to claim 12, wherein the first voltage level is higher than the width and voltage level and the first pulse is shorter than the second pulse width. |
| Claim: |
14. The method according to claim 9, wherein said randomly accessing the memory cell includes actively diverting current flow away from each resistive memory element other than resistive element of the randomly accessed memory cell. |
| Claim: |
15. An electronic memory, comprising: a plurality of memory cells, each memory cell composed of a switch connected in parallel with a resistive memory element; a plurality of bit lines forming columns electrically coupling memory cells in series, the memory cells along at least two columns having substantially the same spacing; a plurality of word lines forming rows and coupled to the switches of the memory cells along the word lines; and circuitry coupled to said bit lines and word lines to write and read data to and from at least one memory cell. |
| Claim: |
16. The method according to claim 15, wherein the memory elements of the memory cells connected along each bit line are connected in series. |
| Claim: |
17. The method according to claim 15, further comprising a select switch connected along each bit line on one side of the memory cells connected along the respective bit line. |
| Claim: |
18. The method according to claim 17, further comprising a sense switch connected along each bit line on an opposite side of the memory cells connected along the respective bit line from said select switch. |
| Claim: |
19. An electronic memory cell comprising: a switch; and a resistive memory element coupled in parallel with said switch. |
| Claim: |
20. The method according to claim 19, wherein said switch is a transistor. |
| Claim: |
21. The method according to claim 19, wherein said resistive memory element is composed of a thin film, resistive material. |
| Claim: |
22. The method according to claim 21, wherein the resistive material is composed of high temperature superconductor material. |
| Claim: |
23. The method of claim 21, wherein the resistive material is composed of colossal magnetoresistive material. |
| Claim: |
24. The method of claim 19, wherein the resistive material is composed of Pr0.7Ca0.3MnO3. |
| Claim: |
25. The method of claim 19, wherein said switch and resistive memory element reside in an area less than about 4 F2. |
| Claim: |
26. A method for reading data from an electronic memory having memory cells arranged in rows of word lines and columns of bit lines, each bit line being connected to a column of memory cells having a switch in parallel with a resistive memory element and each word line being connected to switches in rows of the memory cells, said method comprising: applying a voltage level to all but one word line to turn on each of the switches of the memory cells connected thereto; applying a voltage level to the one remaining word line to turn off the switch of the corresponding memory cell to access that memory cell; applying a voltage level to a first side of a bit line of the memory cell being accessed; and sensing the voltage level on the bit line on a second, opposite side of the memory cell being accessed. |
| Claim: |
27. The method of claim 25, wherein said applying the voltage line to the first side of the bit line includes applying a voltage level below a threshold value that would alter resistance of the resistive memory element. |
| Claim: |
28. The method of claim 27, further comprising accessing the first side of the bit line prior to applying the voltage level to the bit line. |
| Claim: |
29. The method of claim 25, further comprising accessing the second side of the bit line prior to sensing the voltage level. |
| Claim: |
30. An electronic system, comprising: an electronic memory, including: a switch; and a resistive memory element coupled in parallel with said switch; and a processor in communication with said memory to write data to and read data from the electronic memory. |
| Claim: |
31. The electronic system according to claim 30, wherein the electronic system is configured as a communication device. |
| Claim: |
32. The electronic system according to claim 30, wherein the electronic system is configured as a computing device. |
| Claim: |
33. A method of manufacturing an integrated circuit electronic memory, said method comprising: forming a plurality of transistors; forming an insulating layer above the transistors; depositing a resistive material on the insulating layer; etching the resistive material to form a resistive element associated with each of the transistors; etching the insulating layer between the resistive elements to form vias through to the active areas of the transistors; and depositing a conductor in the vias to connect said transistors to the resistive elements. |
| Claim: |
34. The method according to claim 33, wherein each of said transistors and its associated resistive element forms a memory cell having a maximum size of approximately 4 F2. |
| Claim: |
35. The method according to claim 34, further comprising depositing a non-conductive, buffer material on the insulating layer prior to depositing the resistive material such that the resistive material is deposited on the buffer material. |
| Claim: |
36. The method according to claim 33, wherein the resistive material is composed of at least one of colossal magnetoresistance, high temperature superconductor, and PCMO. |
| Claim: |
37. The method of claim 36, wherein the PCMO is composed of Pr0.7Ca0.3MnO3. |
| Claim: |
38. An integrated circuit electronic memory, comprising: a substrate; a transistor disposed on the substrate; an insulating layer disposed above the transistor; a resistive element disposed on the insulating layer above the transistor; and at least two conductors electronically connecting said transistor in parallel with said resistive element. |
| Claim: |
39. The method according to claim 38, wherein said transistor and resistive element forms a memory cell having a maximum size of approximately 4 F2. |
| Claim: |
40. The method according to claim 38, further comprising a non-conductive, buffer material disposed on the insulating layer such that the resistive material is disposed on the buffer material. |
| Claim: |
41. The method according to claim 38, wherein the resistive material is composed of at least one of colossal magnetoresistance, high temperature superconductor, and PCMO. |
| Claim: |
42. The method of claim 41, wherein the PCMO is composed of Pr0.7Ca0.3MnO3. |
| Current U.S. Class: |
365158/000 |
| رقم الانضمام: |
edspap.20050248978 |
| قاعدة البيانات: |
USPTO Patent Applications |