التفاصيل البيبلوغرافية
| العنوان: |
Phase-locked loop circuit with switched-capacitor conditioning of the control current |
| Document Number: |
20050001689 |
| تاريخ النشر: |
January 6, 2005 |
| Appl. No: |
10/798244 |
| Application Filed: |
March 11, 2004 |
| مستخلص: |
A phase-locked loop circuit provides an output signal having a frequency depending on the frequency of a reference signal. The circuit includes a feedback circuit that derives a feedback signal from the output signal, a phase frequency detector that provides a control signal indicative of a phase difference between the reference signal and the feedback signal, a control circuit that controls the frequency of the output signal according to the control signal, and a conditioning circuit that conditions the control signal through a conditioning signal. The conditioning circuit includes a storage circuit that stores energy provided by the control signal and the conditioning signal during a first phase and transfers the accumulated energy to the control circuit during a second phase. |
| Inventors: |
Albasini, Guido Gabriele (Voghera, IT); Milani, Enrico Temporiti (Pavia, IT); Ricotti, Giulio (Broni, IT); Frattini, Giovanni (Torre D'lsola, IT) |
| Assignees: |
STMicroelectronics S.r.l. (Agrate Brianza, IT) |
| Claim: |
1. A phase-locked loop circuit for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit comprising: means for deriving a feedback signal from the output signal; means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal; means for controlling the frequency of the output signal according to the control signal; and means for conditioning the control signal through a conditioning signal, wherein the means for conditioning includes means for accumulating energy provided by the control signal and the conditioning signal during a first phase and for transferring the accumulated energy to the means for controlling the frequency of the output signal during a second phase. |
| Claim: |
2. The circuit according to claim 1, wherein the means for conditioning includes capacitive means, first switching means responsive to a first enabling signal for coupling the capacitive means with the means for providing the control signal during the first phase, and second switching means responsive to a second enabling signal for coupling the capacitive means with the means for controlling the frequency of the output signal during the second phase. |
| Claim: |
3. The circuit according to claim 1, wherein the phase-locked loop circuit is of the fractional type for synthesizing the output signal multiplying the frequency of the reference signal by a fractional conversion factor, the means for deriving the feedback signal including means for dividing the frequency of the output signal by a dividing ratio being modulated to provide the conversion factor on the average, and wherein the means for conditioning includes means for providing a first conditioning signal for compensating a phase error caused by the modulation of the dividing ratio, the control signal consisting of a series of pulses modulated according to a first technique and the first conditioning signal consisting of a series of pulses modulated according to a second technique. |
| Claim: |
4. The circuit according to claim 3, further including means for providing a correction value indicative of the phase error, the correction value having at least one bit, and wherein the means for providing the first conditioning signal includes a digital-to-analog converter of a switched-capacitor type for converting the correction value into the first conditioning signal, the converter being controlled by the first and the second enabling signals. |
| Claim: |
5. The circuit according to claim 4, wherein the converter includes an output capacitor and, for each bit of the correction value, an input capacitor, a first switch for connecting the input capacitor to a power supply source in response to the second enabling signal and the corresponding bit, and a second switch for connecting the input capacitor to the output capacitor in response to the first enabling signal, the conditioning means including a further first switch for connecting the output capacitor to the means for providing the control signal in response to the first enabling signal and a further second switch for connecting the output capacitor to the means for controlling the frequency of the output signal in response to the second enabling signal. |
| Claim: |
6. The circuit according to claim 4, wherein the converter includes, for each bit of the correction value, an input capacitor, a first switch for connecting the input capacitor to a power supply source in response to the first enabling signal and the corresponding bit, and a second switch for connecting the input capacitor to the means for controlling the frequency of the output signal in response to the second enabling signal, the conditioning means including a further capacitor, a further first switch for connecting the further capacitor to the means for providing the control signal in response to the first enabling signal, and a further second switch for connecting the further capacitor to the means for controlling the frequency of the output signal in response to the second enabling signal. |
| Claim: |
7. The circuit according to claim 4, wherein the correction value includes a plurality of bits, the converter further including means for converting the bits of the correction value into a plurality of thermometric bits of even weight. |
| Claim: |
8. The circuit according to claim 7, wherein the converter further includes means for scrambling the thermometric bits. |
| Claim: |
9. The circuit according to claim 1, wherein the means for conditioning includes means for providing a second conditioning signal for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference, the control signal consisting of a series of pulses and the second conditioning signal having a constant amplitude corresponding to the pre-defined phase difference. |
| Claim: |
10. In a fractional-type phase-locked loop circuit, a method of providing an output signal having a frequency depending on the frequency of a reference signal, the method comprising the steps of: deriving a feedback signal from the output signal; providing a control signal indicative of a phase difference between the reference signal and the feedback signal; controlling the frequency of the output signal according to the control signal; and conditioning the control signal through a conditioning signal, wherein accumulating energy provided by the control signal and the conditioning signal during a first phase, and transferring the accumulated energy for controlling the frequency of the output signal during a second phase. |
| Claim: |
11. A phase-locked loop circuit for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit comprising: a charge pump generator including an output terminal; a signal filter; and a first compensation circuit connected to an intermediate node between the output terminal of the charge pump generator and the signal filter, the first compensation circuit including: a plurality of energy storage legs connected to the intermediate node and controlled by respective bits of a digital compensation signal, each energy storage leg being structured to store charge during a first phase if the bit controlling the energy storage leg is active and output the stored charge during a second phase. |
| Claim: |
12. The circuit of claim 11, wherein the first compensation circuit further includes a first capacitor connected between the energy storage legs and the intermediate node. |
| Claim: |
13. The circuit of claim 12, wherein the first compensation circuit further includes an amplifier connected between the energy storage legs and the intermediate node, the first capacitor being connected between an input and an output of the amplifier. |
| Claim: |
15. The circuit of claim 12 wherein the first compensation circuit further includes a first switch connected between the output of the charge pump and a first plate of the first capacitor and a second switch connected between the first plate of the first capacitor and the signal filter, the first and second switches being driven in phase opposition. |
| Claim: |
16. The circuit of claim 15 wherein each energy storage leg includes a second capacitor, a third switch connected between the second capacitor and the first capacitor, and a fourth switch connected between the second capacitor and a voltage reference; the first and third switches being controlled by a first control signal to open and close in tandem, and the second and fourth switches being controlled by a second control signal to open and close in tandem and in opposition to the first and third switches. |
| Claim: |
17. The circuit of claim 11 wherein each energy storage leg includes: an energy storage element; a switch connected between a voltage reference and the energy storage element; and an AND gate having a first input receiving the respective bit of the digital compensation signal, a second input receiving a phase control signal, and an output connected to a control terminal of the switch. |
| Claim: |
18. The circuit of claim 11, further including a second compensation circuit connected between the output of the charge pump and the signal filter, the second compensation circuit including a first energy storage element. |
| Claim: |
19. The circuit of claim 18 wherein the second compensation circuit further includes a first switch connected between the output of the charge pump and the first energy storage element and a second switch connected between the first energy storage element and the signal filter, the first and second switches being driven in phase opposition. |
| Claim: |
20. The circuit of claim 19 wherein each energy storage leg includes a second energy storage element, a third switch connected between the intermediate node and the second energy storage element, and a fourth switch connected between the second energy storage element and a voltage reference; the first and fourth switches being controlled by a first control signal to open and close in tandem, and the second and third switches being controlled by a second control signal to open and close in tandem and in opposition to the first and fourth switches. |
| Current U.S. Class: |
331016/000 |
| رقم الانضمام: |
edspap.20050001689 |
| قاعدة البيانات: |
USPTO Patent Applications |