Electronic Resource
Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements
| العنوان: | Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements |
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| المؤلفون: | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions, Crespo Yepes, Albert, Ramos Hortal, Regina, Barajas Ojeda, Enrique, Aragonès Cervera, Xavier, Mateo Peña, Diego, Martin Martínez, Javier, Rodríguez Martínez, Rosana, Nafría Maqueda, Montserrat |
| بيانات النشر: | 2021-10-01 |
| نوع الوثيقة: | Electronic Resource |
| مستخلص: | ©2021 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 In this work, an ‘on-the-fly’ measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In our experiments, the inversion voltage (VINV) shifts measured during the application of pulsed voltage stresses at the input. It is demonstrated that the shifts can be described by a power law that accounts for the stress time and voltage dependences. Moreover, the circuit degradation has been correlated to the NMOS and PMOS degradations. The results show that the degradation of the CMOS inverter can be evaluated from an analytical equation that considers only the shifts of two parameters (threshold voltage VTH, and mobility µ) of the two transistors in the inverter. Postprint (author's final draft) |
| مصطلحات الفهرس: | Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència::Convertidors de corrent elèctric, Electric inverters, Metal oxide semiconductors, Complementary, CMOS technology, On-the-fly stress characterization, Circuit performance degradation, Transistor aging, CMOS inverters, Measurement technique, Analytical modelling, Convertidors continu-altern, Metall-òxid-semiconductors complementaris, Article |
| URL: | |
| الاتاحة: | Open access content. Open access content Attribution-NonCommercial-NoDerivs 4.0 International ©2021. Elsevier https://creativecommons.org/licenses/by-nc-nd/4.0 Open Access |
| ملاحظة: | application/pdf English |
| Other Numbers: | HGF oai:upcommons.upc.edu:2117/366511 Crespo, A. [et al.]. Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly' measurements. "Solid-state electronics", 1 Octubre 2021, vol. 184, núm. article 108094. 0038-1101 10.1016/j.sse.2021.108094 1331653310 |
| المصدر المساهم: | UNIV POLITECNICA DE CATALUNYA From OAIster®, provided by the OCLC Cooperative. |
| رقم الانضمام: | edsoai.on1331653310 |
| قاعدة البيانات: | OAIster |
| الوصف غير متاح. |