Electronic Resource
MODULARIZATION OF TRIPLE FAULT-TOLERANT DESIGNS (TFTD)
| العنوان: | MODULARIZATION OF TRIPLE FAULT-TOLERANT DESIGNS (TFTD) |
|---|---|
| المؤلفون: | Loomis, Herschel H., Newman, James H., Space Systems Academic Group (SP), Archer, Stuart C. |
| بيانات النشر: | Monterey, CA; Naval Postgraduate School 2020-02-20T01:29:13Z 2020-02-20T01:29:13Z 2019-12 |
| نوع الوثيقة: | Electronic Resource |
| مستخلص: | The configurable fault-tolerant processor (CFTP) project was intended to develop the means for a system to operate in areas which include frequent single-effect events (SEEs) similar to those caused by ionized radiation colliding with logic gates. Such errors are capable of degrading the functionality of a system and completely changing a state machine, such as is at the heart of most spacecrafts’ processors. The method for this consisted of a field-programmable gate array (FPGA) being designed into a system which is capable of detecting and then correcting SEEs. The system was designed by many students. This project will take that design, which launched into space earlier this year, and reduce it to modules which can be uploaded individually, built around a core which will be part of the existing triple fault-tolerant design (TFTD). Modularizing the code allows more experiments to be simultaneously performed in the future by changing the architecture of the system to upload specific modules to specified addresses. This will allow smaller uploads and code tweaks, without incurring long upload times, and more frequent updates to run specific tests ad hoc. Research and development conducted for this thesis has demonstrated the capability to inject configuration errors into the current design and the TFTD’s ability to detect those and similar errors, contributing to a better understanding of the TFTD. http://archive.org/details/modularizationof1094563984 Lieutenant, United States Navy Approved for public release; distribution is unlimited. |
| مصطلحات الفهرس: | configurable fault tolerant processor (CFTP), global triple-modular redundancy (GTMR), NPSAT-1, field-programmable gate array (FPGA), single event effect (SEE), cache, memory controller, error mitigation, hardware design, softcore design, triple fault-tolerant design (TFTD), Thesis |
| URL: | |
| الاتاحة: | Open access content. Open access content This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. |
| ملاحظة: | application/pdf |
| Other Numbers: | AD# oai:calhoun.nps.edu:10945/63984 32075 1142091854 |
| المصدر المساهم: | NAVAL POSTGRADUATE SCH From OAIster®, provided by the OCLC Cooperative. |
| رقم الانضمام: | edsoai.on1142091854 |
| قاعدة البيانات: | OAIster |
| الوصف غير متاح. |