Electronic Resource
Physical vs. physically-aware estimation flow: case study of design space exploration of adders
| العنوان: | Physical vs. physically-aware estimation flow: case study of design space exploration of adders |
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| المؤلفون: | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Ratkovic, Ivan, Palomar Pérez, Óscar, Stanic, Milan, Unsal, Osman Sabri, Cristal Kestelman, Adrián, Valero Cortés, Mateo |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE) 2014 |
| نوع الوثيقة: | Electronic Resource |
| مستخلص: | Selecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power (metrics of interest) depends on the phase of the design flow and the fidelity of the models. In this research, we use design space exploration of low-power adders as a case study for comparative analysis of two estimation flows: Physical layout Aware Synthesis (PAS) and Place and Route (PnR). We study and compare post-PAS and post-PnR estimations of the metrics of interest and the impact of various design parameters and input switching activity factor (aI). Adders are particularly interesting for this study because they are fundamental microprocessor units, and their designinvolves many parameters that create a vast design space. We show cases when the post-PAS and post-PnR estimations could lead to different design decisions, especially from a low-power designer point of view. Our experiments reveal that post-PAS results underestimate the side-effects of clock-gating, pipelining, and extensive timing optimizations compared to post-PnR results. We also observe that PnR estimation flow sometimes reports counterintuitive results Peer Reviewed Postprint (published version) |
| مصطلحات الفهرس: | Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència, Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics, Power electronics, Integrated circuits, Adder, Design space exploration, Estimation method, Low-power, Physical layout aware synthesis, Place and route, Electrònica de potència, Circuits integrats, Conference report |
| URL: | |
| الاتاحة: | Open access content. Open access content Attribution-NonCommercial-NoDerivs 3.0 Spain http://creativecommons.org/licenses/by-nc-nd/3.0/es Restricted access - publisher's policy |
| ملاحظة: | 6 p. application/pdf English |
| Other Numbers: | HGF oai:upcommons.upc.edu:2117/24800 Ratkovic, I. [et al.]. Physical vs. physically-aware estimation flow: case study of design space exploration of adders. A: IEEE Computer Society Annual Symposium on VLSI. "ISVLSI 2014: 2014 IEEE Computer Society Annual Symposium on VLSI: 9-11 July 2014: Tampa, Florida". Tampa: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 118-123. 978-1-4799-3763-9 10.1109/ISVLSI.2014.14 1132974922 |
| المصدر المساهم: | UNIV POLITECNICA DE CATALUNYA From OAIster®, provided by the OCLC Cooperative. |
| رقم الانضمام: | edsoai.on1132974922 |
| قاعدة البيانات: | OAIster |
| الوصف غير متاح. |