Electronic Resource
Floating-Point Sparse Matrix-Vector Multiply for FPGAs
| العنوان: | Floating-Point Sparse Matrix-Vector Multiply for FPGAs |
|---|---|
| المؤلفون: | Schmit, Herman, Wilton, Steve, deLorimier, Michael, DeHon, André |
| بيانات النشر: | ACM 2005-02 |
| نوع الوثيقة: | Electronic Resource |
| مستخلص: | Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Multiply (SMVM) kernel. In fact, it is not uncommon for microprocessors to yield only 10–20% of their peak floating-point performance when computing SMVM. We develop and analyze a scalable SMVM implementation on modern FPGAs and show that it can sustain high throughput, near peak, floating-point performance. For benchmark matrices from the Matrix Market Suite we project 1.5 double precision Gflops/FPGA for a single Virtex II 6000-4 and 12 double precision Gflops for 16 Virtex IIs (750Mflops/FPGA). |
| مصطلحات الفهرس: | Book Section, PeerReviewed |
| URL: | CaltechAUTHORS:20161006-130031306 10.1145/1046192.1046203 |
| الاتاحة: | Open access content. Open access content |
| ملاحظة: | Floating-Point Sparse Matrix-Vector Multiply for FPGAs |
| Other Numbers: | CIT oai:authors.library.caltech.edu:70921 deLorimier, Michael and DeHon, André (2005) Floating-Point Sparse Matrix-Vector Multiply for FPGAs. In: FPGA '05 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays. ACM , New York, NY, pp. 75-85. ISBN 1-59593-029-9. https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306 <https://resolver.caltech.edu/CaltechAUTHORS:20161006-130031306> 980598057 |
| المصدر المساهم: | CALIFORNIA INST OF TECH From OAIster®, provided by the OCLC Cooperative. |
| رقم الانضمام: | edsoai.ocn980598057 |
| قاعدة البيانات: | OAIster |
| الوصف غير متاح. |