Electronic Resource

Zero-defect designs, why and how: formal verification vs. automated synthesis

التفاصيل البيبلوغرافية
العنوان: Zero-defect designs, why and how: formal verification vs. automated synthesis
المؤلفون: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Politecnico di Torino [Torino] (Polito) ; Politecnico di Torino, Borrione, D., Prinetto, P.
المصدر: Information-Processing-89.-Proceedings-of-the-IFIP-11th-World-Computer-Congress.; Information-Processing-89.-Proceedings-of-the-IFIP-11th-World-Computer-Congress., Dec 1988, San Francisco, CA, France. North-Holland, Amsterdam, Netherlands, pp.233-40
بيانات النشر: HAL CCSD North-Holland, Amsterdam, Netherlands
نوع الوثيقة: Electronic Resource
مستخلص: ISBN: 0444880151
Zero-defect VLSI design is a goal one must try to reach and CAD tools provide an increasingly important support to designers. High-level automated synthesis and formal verification are cooperating approaches to this end. The paper analyzes the general framework of digital design and the relationships between synthesis and verification as far as functional correctness is concerned, showing their limits, mutual dependencies, and how they can and should work together.
مصطلحات الفهرس: zero-defect-VLSI-design, equivalence-preserving-transformations, formal-verification, automated-synthesis, CAD-tools, digital-design, functional-correctness, PACS 85.42, [SPI.NANO] Engineering Sciences/Micro and nanotechnologies/Microelectronics, Conference papers
الاتاحة: Open access content. Open access content
ملاحظة: San Francisco, CA, France
Information-Processing-89.-Proceedings-of-the-IFIP-11th-World-Computer-Congress.
English
Other Numbers: RNQ oai:HAL:hal-00014303v1
hal-00014303
893012802
المصدر المساهم: CENTRE NAT DE LA RECHERCHE SCIENTIFIQUE
From OAIster®, provided by the OCLC Cooperative.
رقم الانضمام: edsoai.ocn893012802
قاعدة البيانات: OAIster