Dissertation/ Thesis
Low-Power LNA Design using Forward Body Biasing Technique
| العنوان: | Low-Power LNA Design using Forward Body Biasing Technique |
|---|---|
| Alternate Title: | 利用順向基極偏壓設計之低功耗低雜訊放大器 |
| المؤلفون: | Huang, Jun-Rong, 黃俊榮 |
| Thesis Advisors: | Guo, Jyh-Chyurn, 郭治群 |
| سنة النشر: | 2009 |
| المجموعة: | National Digital Library of Theses and Dissertations in Taiwan |
| الوصف: | 98 In this thesis, low-power low noise amplifiers (LNA) design and fabrication have been realized using RF CMOS technologies for applications in ultra-low power or ultra-wide band (UWB) wireless receivers. The major achievements are composed of two circuit chips. One is UWB low-power LNA, and the other is sub-0.2mW ultra-low power (ULP) LNA. For the UWB LNA adopting three-section band-pass Chebyshev filter, the bandwidth can be extended over 3.1~10.6 GHz, and low power is achieved by using forward body bias (FBB) technique. The input matching to standard 50 ���n was realized through the three-section LC networks adopted in the MOS transistor with inductively degenerated source. This UWB LNA is fabricated in a 0.13-�慆 RF CMOS process. The measured performance over the targeted bandwidth of 3.1~ 10.6GHz indicates that the power gain is 10.8 ~ 5 dB, noise figure is 3.9 ~ 4.1 dB, power consumption is 8.4 mW from 0.9V, the input and output return losses, i.e. S11 and S22 are below -6.7dB and -5.8dB respectively, and the leakage S12 can be kept below -27.3 dB in 3.3 ~ 8.1GHz. The power consumption for this UWB LNA can be effectively reduced by lowering the supply voltage VDD attributed to substantially lower threshold voltage (VT) under forward body biases. As for the ultra-low power LNA design in part two, FBB scheme was implemented in this work using 90nm low leakage (LL) CMOS process. As a result, Sub-0.2mW LNA can be realized based on a cascade topology, in which the MOSFET at transconductance stage is biased under subthreshold condition and applied with FBB. Assuming the availability of on-chip inductors with performance predicted by the model, the VDD can be pushed to as low as 0.18V and sufficient gain can be maintained, attributed to FBB. ADS simulation predicted that this ULP LNA can attain power gain of 11 dB at 1.4GHz and consume extremely low power of 0.19mW from 0.18V. Furthermore, the noise figure (NF50) can reach the minimum of 2.1 dB at near 1.5GHz and keep around 2.3 dB at 1.4GHz. The input and output return losses (S11 and S22) are –10.4dB and –10.5dB, respectively. The port-to-port leakage (S12) is maintained as low as –15.2 dB. The power gain (S21) measured from the real chips under 0.18V is abnormally low, due to poor inductors performance and the resulted severe deviation in input matching. When increasing VDD to 0.5V, this problem can be solved and promisingly good results can be realized. The power gain (S21) is 5.5 dB at 1.4GHz and power consumption is 1.75mW from 0.5V. S11 and S22 are –12.1dB and –14.8dB, respectively, and S12 is as low as –23.5 dB. |
| Original Identifier: | 098NCTU5428034 |
| نوع الوثيقة: | 學位論文 ; thesis |
| وصف الملف: | 113 |
| الاتاحة: | http://ndltd.ncl.edu.tw/handle/47101513637632769150 |
| رقم الانضمام: | edsndl.TW.098NCTU5428034 |
| قاعدة البيانات: | Networked Digital Library of Theses & Dissertations |
| الوصف غير متاح. |