Dissertation/ Thesis
A 622Mb/s Clock and Data Recovery for OC-12 SONET Applications
| العنوان: | A 622Mb/s Clock and Data Recovery for OC-12 SONET Applications |
|---|---|
| Alternate Title: | 應用於OC-12SONET之622Mb/s時脈與資料回復電路 |
| المؤلفون: | Wei-Chun Chou, 周維駿 |
| Thesis Advisors: | Chun-Chieh Chen, 陳淳杰 |
| سنة النشر: | 2006 |
| المجموعة: | National Digital Library of Theses and Dissertations in Taiwan |
| الوصف: | 94 The goal of this thesis is to design a 622Mb/s Clock and Data Recovery (CDR) Circuit for SONET OC-12 optical networks. The CDR circuit is based on the structure of Phase Locked Loop (PLL).And, The function of the CDR circuit is to recover the clock information which is embedded into incoming data and resynchronize it with the incoming data. This thesis could be divided into five chapters. Chapter 1 is introduction. The architecture of CDR and several phase detectors for random data is described in Chapter 2. Chapter 3 discusses the system consideration and the loop behavior model. From the behavior simulation, the CDR transient characteristic can be observed quickly. Thus, the parameters on the CDR can be evaluated as soon as possible. In Chapter 4, each blocks of the CDR circuit are discussed in detail. The Circuits were simulated with TSMC 0.35μm 2p4m CMOS process. Simulation results show that the CDR circuit consumes 36mW from a 3V supply voltage. The rms and peak-to-peak jitter of the output clock are 12.4ps and 59.7ps, respectively. Finally, the conclusion and future work are presented in Chapter 5. |
| Original Identifier: | 094CYCU5428028 |
| نوع الوثيقة: | 學位論文 ; thesis |
| وصف الملف: | 70 |
| الاتاحة: | http://ndltd.ncl.edu.tw/handle/49784061129760082288 |
| رقم الانضمام: | edsndl.TW.094CYCU5428028 |
| قاعدة البيانات: | Networked Digital Library of Theses & Dissertations |
| الوصف غير متاح. |