التفاصيل البيبلوغرافية
| العنوان: |
Multi-Rate Discrete Domain Modeling of Power Hardware-in-The-Loop Setups |
| المؤلفون: |
Fargah Ashrafidehkordi, Dustin Kottonau, Giovanni De Carne |
| المصدر: |
IEEE Open Journal of Power Electronics, Vol 4, Pp 539-548 (2023) |
| بيانات النشر: |
IEEE, 2023. |
| سنة النشر: |
2023 |
| المجموعة: |
LCC:Electrical engineering. Electronics. Nuclear engineering |
| مصطلحات موضوعية: |
Power Hardware In the Loop, digital real-time simulations, power hardware in the loop stability, multi-rate discrete-time sampling, Electrical engineering. Electronics. Nuclear engineering, TK1-9971 |
| الوصف: |
Power Hardware-in-the-Loop (PHIL) facilitates the testing of novel power engineering solutions in the lab, allowing a flexible testing environment while keeping the high testing fidelity of real hardware. Due to the analog/digital intersection of the PHIL setup, selecting simply continuous or single-rate discrete-time domain fails to model such a hybrid system accurately. This article proposes a multi-rate discrete-time modeling approach of a PHIL setup that can estimate the mixed analog and digital nature of the PHIL accurately, resulting in accuracy improvement over a wide range of frequencies. The proposed approach applies two different sampling times, a large one connected to the digital simulator and a small one for modeling the analog-hardware part. Dynamics and delays of interfaces, such as analog-to-digital converters, the power amplifier, the sensor, and the low-pass filter, have been accurately modeled and validated by means of experimental results. |
| نوع الوثيقة: |
article |
| وصف الملف: |
electronic resource |
| اللغة: |
English |
| تدمد: |
2644-1314 |
| Relation: |
https://ieeexplore.ieee.org/document/10144402/; https://doaj.org/toc/2644-1314 |
| DOI: |
10.1109/OJPEL.2023.3283035 |
| URL الوصول: |
https://doaj.org/article/b1afc1c925a14727b2f780fe7223d8f5 |
| رقم الانضمام: |
edsdoj.b1afc1c925a14727b2f780fe7223d8f5 |
| قاعدة البيانات: |
Directory of Open Access Journals |