Academic Journal
Real-Time Localization of Epileptogenic Foci EEG Signals: An FPGA-Based Implementation
| العنوان: | Real-Time Localization of Epileptogenic Foci EEG Signals: An FPGA-Based Implementation |
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| المؤلفون: | Jose V. Frances-Villora, Manuel Bataller-Mompean, Azeddine Mjahad, Alfredo Rosado-Muñoz, Antonio Gutierrez Martin, Vicent Teruel-Marti, Vicente Villanueva, Kevin G. Hampel, Juan F. Guerrero-Martinez |
| المصدر: | Applied Sciences, Vol 10, Iss 3, p 827 (2020) |
| بيانات النشر: | MDPI AG, 2020. |
| سنة النشر: | 2020 |
| المجموعة: | LCC:Technology LCC:Engineering (General). Civil engineering (General) LCC:Biology (General) LCC:Physics LCC:Chemistry |
| مصطلحات موضوعية: | electroencephalogram, epileptic eeg signal classification, epilepsy, epileptogenic focus, real-time implementation, fpga, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999 |
| الوصف: | The epileptogenic focus is a brain area that may be surgically removed to control of epileptic seizures. Locating it is an essential and crucial step prior to the surgical treatment. However, given the difficulty of determining the localization of this brain region responsible of the initial seizure discharge, many works have proposed machine learning methods for the automatic classification of focal and non-focal electroencephalographic (EEG) signals. These works use automatic classification as an analysis tool for helping neurosurgeons to identify focal areas off-line, out of surgery, during the processing of the huge amount of information collected during several days of patient monitoring. In turn, this paper proposes an automatic classification procedure capable of assisting neurosurgeons online, during the resective epilepsy surgery, to refine the localization of the epileptogenic area to be resected, if they have doubts. This goal requires a real-time implementation with as low a computational cost as possible. For that reason, this work proposes both a feature set and a classifier model that minimizes the computational load while preserving the classification accuracy at 95.5%, a level similar to previous works. In addition, the classification procedure has been implemented on a FPGA device to determine its resource needs and throughput. Thus, it can be concluded that such a device can embed the whole classification process, from accepting raw signals to the delivery of the classification results in a cost-effective Xilinx Spartan-6 FPGA device. This real-time implementation begins providing results after a 5 s latency, and later, can deliver floating-point classification results at 3.5 Hz rate, using overlapped time-windows. |
| نوع الوثيقة: | article |
| وصف الملف: | electronic resource |
| اللغة: | English |
| تدمد: | 2076-3417 |
| Relation: | https://www.mdpi.com/2076-3417/10/3/827; https://doaj.org/toc/2076-3417 |
| DOI: | 10.3390/app10030827 |
| URL الوصول: | https://doaj.org/article/e3a0211cf41348dd9b41ac58a9b043b9 |
| رقم الانضمام: | edsdoj.3a0211cf41348dd9b41ac58a9b043b9 |
| قاعدة البيانات: | Directory of Open Access Journals |
Full Text Finder | تدمد: | 20763417 |
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| DOI: | 10.3390/app10030827 |