التفاصيل البيبلوغرافية
| العنوان: |
On VLSI Layouts Of The Star Graph And Related Networks |
| المؤلفون: |
Ondrej Sykora, Imrich Vrtó |
| المساهمون: |
The Pennsylvania State University CiteSeerX Archives |
| المصدر: |
ftp://ftp.ifi.savba.sk/pub/imrich/integrat94.ps.gz |
| سنة النشر: |
1994 |
| المجموعة: |
CiteSeerX |
| مصطلحات موضوعية: |
Key Words, area, arrangement graph, congestion, crossing number, embedding, layout, pancake graph, star graph, VLSI |
| الوصف: |
We prove that the minimal VLSI layout of the arrangement graph A(n; k) occupies \Theta(n!=(n \Gamma k \Gamma 1)!) 2 area. As a special case we obtain an optimal layout for the star graph S n with the area \Theta(n!) 2 : This answers an open problem posed by Akers, Harel and Krishnamurthy [1]. The method is also applied to the pancake graph. The results provide optimal upper and lower bounds for crossing numbers of the above graphs. Key Words: area, arrangement graph, congestion, crossing number, embedding, layout, pancake graph, star graph, VLSI 1 |
| نوع الوثيقة: |
text |
| وصف الملف: |
application/postscript |
| اللغة: |
English |
| Relation: |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.29.372 |
| الاتاحة: |
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.29.372 |
| Rights: |
Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| رقم الانضمام: |
edsbas.D7658BA3 |
| قاعدة البيانات: |
BASE |