التفاصيل البيبلوغرافية
| العنوان: |
Floating-Point Sparse Matrix-Vector Multiply for FPGAs |
| المؤلفون: |
deLorimier, Michael, DeHon, André |
| المساهمون: |
Schmit, Herman, Wilton, Steve |
| المصدر: |
FPGA '05 ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2005, Monterey, CA, February 20-22, 2005 |
| بيانات النشر: |
ACM |
| سنة النشر: |
2005 |
| المجموعة: |
Caltech Authors (California Institute of Technology) |
| مصطلحات موضوعية: |
Algorithm, Performance, Design, Experimentation, Floating Point, FPGA, Reconfigurable Architecture, Sparse Matrix, Compressed Sparse Row |
| الوصف: |
Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not deliver near their peak floating-point performance on efficient algorithms that use the Sparse Matrix-Vector Multiply (SMVM) kernel. In fact, it is not uncommon for microprocessors to yield only 10–20% of their peak floating-point performance when computing SMVM. We develop and analyze a scalable SMVM implementation on modern FPGAs and show that it can sustain high throughput, near peak, floating-point performance. For benchmark matrices from the Matrix Market Suite we project 1.5 double precision Gflops/FPGA for a single Virtex II 6000-4 and 12 double precision Gflops for 16 Virtex IIs (750Mflops/FPGA). ; © 2005 ACM. This work was supported by the Microelectronics Advanced Research Consortium (MARCO) and is part of the efforts of the Gigascale Systems Research Center (GSRC). Thanks to Keith Underwood for valuable editorial comments on this writeup. |
| نوع الوثيقة: |
book part |
| اللغة: |
unknown |
| Relation: |
https://doi.org/10.1145/1046192.1046203; eprintid:70921 |
| DOI: |
10.1145/1046192.1046203 |
| الاتاحة: |
https://doi.org/10.1145/1046192.1046203 |
| Rights: |
info:eu-repo/semantics/closedAccess ; Other |
| رقم الانضمام: |
edsbas.BE1E85E7 |
| قاعدة البيانات: |
BASE |