Academic Journal

Low-Power Design of an Embedded Microprocessor Core

التفاصيل البيبلوغرافية
العنوان: Low-Power Design of an Embedded Microprocessor Core
المؤلفون: Masgonty Arm Durand, J. -m. Masgonty, C. Arm, S. Dur, M. Stegers, T. Schneider, C. Piguet
المساهمون: The Pennsylvania State University CiteSeerX Archives
المصدر: http://www.esscirc.org/papers-96/97.pdf.
سنة النشر: 1996
المجموعة: CiteSeerX
الوصف: Low-power consumption has emerged as a very important issue in the design of integrated circuits in CMOS technology. The basic idea behind low-power RISC-like architectures is to reduce the number of executed instructions and clock cycles for the execution of a given task. In addition to these architectural issues, important power savings have been obtained by lowering the supply voltage, by pipelining, by adopting gated clock techniques as well as by using hierarchical memories. 1. Introduction Low-power CMOS microprocessors and microcontrollers are the key to the realization of portable products in which the power consumption is a more important issue than other performances. Low-power microprocessor cores embedded in ASICs are more and more required in various applications. The design of the low-power microprocessor presented in this paper has been addressed at the behavioral, architectural, logical and physical levels. At the behavioral level, the instruction set has been chosen .
نوع الوثيقة: text
وصف الملف: application/pdf
اللغة: English
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.31.171; http://www.esscirc.org/papers-96/97.pdf
الاتاحة: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.31.171
http://www.esscirc.org/papers-96/97.pdf
Rights: Metadata may be used without restrictions as long as the oai identifier remains attached to it.
رقم الانضمام: edsbas.B6C49613
قاعدة البيانات: BASE