التفاصيل البيبلوغرافية
| العنوان: |
Geometrically-constrained, parasitic-aware synthesis of analog ICs |
| المؤلفون: |
Castro López, Rafael, Fernández Fernández, Francisco Vidal, Rodríguez Vázquez, Ángel Benito |
| المساهمون: |
Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
| بيانات النشر: |
The International Society for Optical Engineering - SPIE |
| سنة النشر: |
2020 |
| المجموعة: |
idUS - Deposito de Investigación Universidad de Sevilla |
| مصطلحات موضوعية: |
Analog CAD, Floorplan Sizing, Layout Parasitics, Layout Templates, Layout-Aware Synthesis |
| الوصف: |
In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how. ; Ministerio de Educación y Ciencia TEC2004-01752 |
| نوع الوثيقة: |
conference object |
| اللغة: |
English |
| Relation: |
VLSI Circuits and Systems II (2005), p 673-684; TEC2004-01752; http://dx.doi.org/10.1117/12.607933; https://idus.us.es/handle//11441/92294 |
| الاتاحة: |
https://idus.us.es/handle//11441/92294 |
| Rights: |
Attribution-NonCommercial-NoDerivatives 4.0 Internacional ; http://creativecommons.org/licenses/by-nc-nd/4.0/ ; info:eu-repo/semantics/openAccess |
| رقم الانضمام: |
edsbas.89A35D7 |
| قاعدة البيانات: |
BASE |