Academic Journal
Non-stalling counterflow architecture
| العنوان: | Non-stalling counterflow architecture |
|---|---|
| المؤلفون: | Michael F. Miller, Kennneth J. Janik, Shih-lien Lu |
| المساهمون: | The Pennsylvania State University CiteSeerX Archives |
| المصدر: | http://computer.org/tab/tcca/HPCA-4/miller.pdf. |
| سنة النشر: | 1998 |
| المجموعة: | CiteSeerX |
| الوصف: | The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making and localized clocking and data movement. We have taken these ideas and reformulated them into a substantially faster more scalable architecture that has the same distributed decision making and locality for clocking and data, but adds very aggressive speculation, no stalls, and other desirable characteristics. A high level Java simulator has been build to explore the design tradeoffs and evaluate performance. Keywords-- counterflow, CFPP, pipeline, dataflow, virtual register, VRP, counterdataflow, CDF, multithreading, architecture. |
| نوع الوثيقة: | text |
| وصف الملف: | application/pdf |
| اللغة: | English |
| Relation: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.76.3495; http://computer.org/tab/tcca/HPCA-4/miller.pdf |
| الاتاحة: | http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.76.3495 http://computer.org/tab/tcca/HPCA-4/miller.pdf |
| Rights: | Metadata may be used without restrictions as long as the oai identifier remains attached to it. |
| رقم الانضمام: | edsbas.89654697 |
| قاعدة البيانات: | BASE |
| الوصف غير متاح. |