Conference
Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
| العنوان: | Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment |
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| المؤلفون: | M. Pivanti, M. Sozzi, SCHIFANO, Sebastiano Fabio, DALPIAZ, Pietro, GAMBERINI, Enrico, GIANOLI, Alberto |
| المساهمون: | M., Pivanti, Schifano, Sebastiano Fabio, Dalpiaz, Pietro, Gamberini, Enrico, Gianoli, Alberto, M., Sozzi |
| بيانات النشر: | D.L. Groep and D. Bonacorsi |
| سنة النشر: | 2014 |
| المجموعة: | Università degli Studi di Ferrara: CINECA IRIS |
| الوصف: | Lowest level (sometimes called Level 0, L0) triggers are fundamental components in high energy physics experiments, and yet they are quite often custom-made. Even when using FPGAs to achieve better flexibility in modifying and maintaining, small changes require hardware reconfiguration and changes to the algorithm logic could be constrained by the hardware. For these reasons we are developing for the NA62 experiment at CERN a L0-trigger based on the use of a PC and commodity FPGA development board. |
| نوع الوثيقة: | conference object |
| وصف الملف: | ELETTRONICO |
| اللغة: | English |
| Relation: | info:eu-repo/semantics/altIdentifier/wos/000342287200008; International Conference on Computing in High Energy and Nuclear Physics; volume:513; firstpage:012008; lastpage:012008; journal:JOURNAL OF PHYSICS. CONFERENCE SERIES; http://hdl.handle.net/11392/2008412; info:eu-repo/semantics/altIdentifier/scopus/2-s2.0-84903612193; http://stacks.iop.org/1742-6596/513/i=1/a=012008 |
| DOI: | 10.1088/1742-6596/513/1/012008 |
| الاتاحة: | http://hdl.handle.net/11392/2008412 https://doi.org/10.1088/1742-6596/513/1/012008 http://stacks.iop.org/1742-6596/513/i=1/a=012008 |
| رقم الانضمام: | edsbas.88A5C571 |
| قاعدة البيانات: | BASE |
| DOI: | 10.1088/1742-6596/513/1/012008 |
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