Conference
Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing
| العنوان: | Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing |
|---|---|
| المؤلفون: | Devic, Guillaume, France-Pillois, Maxime, Salles, Jérémie, Sassatelli, Gilles, Gamatié, Abdoulaye |
| المساهمون: | ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS) |
| المصدر: | NEWCAS 2021 - 19th IEEE International New Circuits and Systems Conference ; https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639 ; NEWCAS 2021 - 19th IEEE International New Circuits and Systems Conference, Jun 2021, Toulon (virtual), France. pp.1-4, ⟨10.1109/NEWCAS50681.2021.9462745⟩ ; https://newcas2021.univ-tln.fr/ |
| بيانات النشر: | HAL CCSD |
| سنة النشر: | 2021 |
| المجموعة: | Université de Montpellier: HAL |
| مصطلحات موضوعية: | Multiply-and-Accumulate units, MAC, Machine Learning, Edge-Computing, Quantization, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] |
| جغرافية الموضوع: | Toulon (virtual), France |
| الوصف: | International audience ; Machine learning algorithms are compute-and memory-intensive. Their execution at the edge on resourceconstrained embedded systems is challenging. Data quantization, i.e. data bit-width reduction, contributes to reducing de-facto the memory bandwidth requirement. In order to best exploit this bit-width reduction, a prevailing approach consists of tailored hardware accelerators. Another approach relies on generalpurpose compute units with Single Instruction Multiple Data (SIMD) support for reduced data bit-width precision, as in ARM Cortex-M [1] or RISC-V based RI5CY [2] processors. However, such processors only handle a few predefined bit-width ranges, e.g. 8-bit and 16-bit only for the ARM SIMD. This paper proposes a flexible architecture of Multiply-and-Accumulate (MAC) unit allowing asymmetric multiplication for operand sizes in powers of 2, up to 32 bits. The synthesis of this architecture in 28nm FD-SOI technology shows 10% and 25% reduction in area and dynamic power respectively, compared to the RI5CY MAC unit. From the energy-efficiency point of view, up to 50% improvements are achieved. |
| نوع الوثيقة: | conference object |
| اللغة: | English |
| Relation: | lirmm-03241639; https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639; https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639/document; https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639/file/NEWCAS_2021_Highly-Adaptive%20Mixed-Precision%20MAC%20Unit%20for%20Smart%20and%20Low-Power%20Edge%20Computing.pdf |
| DOI: | 10.1109/NEWCAS50681.2021.9462745 |
| الاتاحة: | https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639 https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639/document https://hal-lirmm.ccsd.cnrs.fr/lirmm-03241639/file/NEWCAS_2021_Highly-Adaptive%20Mixed-Precision%20MAC%20Unit%20for%20Smart%20and%20Low-Power%20Edge%20Computing.pdf https://doi.org/10.1109/NEWCAS50681.2021.9462745 |
| Rights: | info:eu-repo/semantics/OpenAccess |
| رقم الانضمام: | edsbas.5B3664F |
| قاعدة البيانات: | BASE |
| DOI: | 10.1109/NEWCAS50681.2021.9462745 |
|---|