Dissertation/ Thesis
Data locality on manycore architectures ; Optimisation de la localité des données sur architectures manycœurs
| العنوان: | Data locality on manycore architectures ; Optimisation de la localité des données sur architectures manycœurs |
|---|---|
| المؤلفون: | Amstel, Duco Van |
| المساهمون: | Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria), Université Grenoble Alpes, Fabrice Rastello |
| المصدر: | https://theses.hal.science/tel-01358312 ; Architectures Matérielles [cs.AR]. Université Grenoble Alpes, 2016. Français. ⟨NNT : 2016GREAM019⟩. |
| بيانات النشر: | CCSD |
| سنة النشر: | 2016 |
| المجموعة: | Université Grenoble Alpes: HAL |
| مصطلحات موضوعية: | Code optimisation, Data locality, Scheduling, Loop tiling, Dataflow languages, Manycore architectures, Optimisation de code, Localité des données, Ordonnancement, Pavage de boucles, Langages dataflow, Architectures manycœurs, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] |
| الوصف: | The continuous evolution of computer architectures has been an important driver of research in code optimization and compiler technologies. A trend in this evolution that can be traced back over decades is the growing ratio between the available computational power (IPS, FLOPS, .) and the corresponding bandwidth between the various levels of the memory hierarchy (registers, cache, DRAM). As a result the reduction of the amount of memory communications that a given code requires has been an important topic in compiler research. A basic principle for such optimizations is the improvement of temporal data locality: grouping all references to a single data-point as close together as possible so that it is only required for a short duration and can be quickly moved to distant memory (DRAM) without any further memory communications.Yet another architectural evolution has been the advent of the multicore era and in the most recent years the first generation of manycore designs. These architectures have considerably raised the bar of the amount of parallelism that is available to programs and algorithms but this is again limited by the available bandwidth for communications between the cores. This brings some issues thatpreviously were the sole preoccupation of distributed computing to the world of compiling and code optimization techniques.In this document we present a first dive into a new optimization technique which has the promise of offering both a high-level model for data reuses and a large field of potential applications, a technique which we refer to as generalized tiling. It finds its source in the already well-known loop tiling technique which has been applied with success to improve data locality for both register and cache-memory in the case of nested loops. This new "flavor" of tiling has a much broader perspective and is not limited to the case of nested loops. It is build on a new representation, the memory-use graph, which is tightly linked to a new model for both memory usage and communication ... |
| نوع الوثيقة: | doctoral or postdoctoral thesis |
| اللغة: | French |
| Relation: | NNT: 2016GREAM019 |
| الاتاحة: | https://theses.hal.science/tel-01358312 https://theses.hal.science/tel-01358312v2/document https://theses.hal.science/tel-01358312v2/file/VANAMSTEL_2016_archivage.pdf |
| Rights: | info:eu-repo/semantics/OpenAccess |
| رقم الانضمام: | edsbas.590BF546 |
| قاعدة البيانات: | BASE |
| الوصف غير متاح. |