التفاصيل البيبلوغرافية
| العنوان: |
Performance Improvement of MIPS Architecture by Adding New Features |
| المؤلفون: |
Galani Tina, R.D.Daruwala |
| المصدر: |
International Journal of Advanced Research in Computer Science and Software Engineering, 3(2), 423-430, (2013-02-05) |
| بيانات النشر: |
Zenodo |
| سنة النشر: |
2013 |
| المجموعة: |
Zenodo |
| مصطلحات موضوعية: |
MIPS Processor, Reduced Instruction Set Computer (RISC), VHDL, Pipeline, Xilinx 12.1, FPGA |
| الوصف: |
RISC or Reduced Instruction Set Computer is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. This paper targets to develop a 32- bit MIPS RISC processor architecture in VHDL language that detects the pipeline hazards during the multithreading and reduce Cycle per instruction (CPI) by eliminating the pipeline hazards. The module functionality and performance issue like area, power dissipation and propagation delay are analysed at 90nm process technology using Virtex4 XC4VLX15 XILINX tool. |
| نوع الوثيقة: |
article in journal/newspaper |
| اللغة: |
unknown |
| Relation: |
https://doi.org/; https://doi.org/10.5281/zenodo.32432; oai:zenodo.org:32432 |
| DOI: |
10.5281/zenodo.32432 |
| الاتاحة: |
https://doi.org/10.5281/zenodo.32432 |
| Rights: |
info:eu-repo/semantics/openAccess ; Creative Commons Attribution 4.0 International ; https://creativecommons.org/licenses/by/4.0/legalcode |
| رقم الانضمام: |
edsbas.564BADA |
| قاعدة البيانات: |
BASE |