Conference
A novel ultra high speed and configurable discrete wavelet packet transform architecture
| العنوان: | A novel ultra high speed and configurable discrete wavelet packet transform architecture |
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| المؤلفون: | Chehaitly, Mouhamad, Tabaa, Mohamed, Monteiro, Fabrice, Dandache, Abbas, Alaeddine, Ali, Hamie, Ali, Fadlallah, Mouenes |
| المساهمون: | Laboratoire de Génie Industriel, de Production et de Maintenance (LGIPM), Université de Lorraine (UL), Laboratoire Pluridisciplinaire de Recherche et Innovation (LPRI), Ecole Marocaine des Sciences de l'Ingénieur (EMSI), الجامعة اللبنانية بيروت = Lebanese University Beirut = Université libanaise Beyrouth (LU / ULB) |
| المصدر: | 2016 28th International Conference on Microelectronics (ICM) https://hal.univ-lorraine.fr/hal-03673046 2016 28th International Conference on Microelectronics (ICM), Dec 2016, Giza, Egypt. pp.289-292, ⟨10.1109/ICM.2016.7847872⟩ |
| بيانات النشر: | CCSD IEEE |
| سنة النشر: | 2016 |
| المجموعة: | Université de Lorraine: HAL |
| مصطلحات موضوعية: | Finite impulse response filters, Filter banks, Filtering theory, Computer architecture, Discrete wavelet transforms, [SPI.TRON]Engineering Sciences [physics]/Electronics, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing |
| جغرافية الموضوع: | Giza, Egypt |
| الوصف: | International audience ; This work is dedicated to present a new architecture of Discrete Wavelet Packet Transform (DWPT) implemented in FPGA using a parallel direct FIR () filter. The main target of our architecture is to provide an effective performance trade-off, where it significantly increases the throughput with a restricted amount of hardware. It is smartly connect based on low-pass and high-pass filters in the Mallat-tree algorithm by a clever sharing of the hardware resources. This architecture is fully configurable in synthesis according to parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient. Consequently, the simulation results accelerated to an approximate value of P*(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV - (FPGA) and it was developed in VHDL at RTL level modeling. |
| نوع الوثيقة: | conference object |
| اللغة: | English |
| DOI: | 10.1109/ICM.2016.7847872 |
| الاتاحة: | https://hal.univ-lorraine.fr/hal-03673046 https://doi.org/10.1109/ICM.2016.7847872 |
| رقم الانضمام: | edsbas.44A11F40 |
| قاعدة البيانات: | BASE |
| DOI: | 10.1109/ICM.2016.7847872 |
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