Dissertation/ Thesis
Reliability mechanisms in Trigate/nanowire transistors ; Etude des mécanismes de fiabilité sur transistors Trigate/Nanowire
| العنوان: | Reliability mechanisms in Trigate/nanowire transistors ; Etude des mécanismes de fiabilité sur transistors Trigate/Nanowire |
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| المؤلفون: | Laurent, Antoine |
| المساهمون: | Laboratoire d'Informatique pour la Mécanique et les Sciences de l'Ingénieur (LIMSI), Université Paris Saclay (COmUE)-Centre National de la Recherche Scientifique (CNRS)-Sorbonne Université - UFR d'Ingénierie (UFR 919), Sorbonne Université (SU)-Sorbonne Université (SU)-Université Paris-Saclay-Université Paris-Sud - Paris 11 (UP11), Communauté Université Grenoble Alpes, Gérard Ghibaudo, Xavier Garros (co-encadrant), David Roy (co-encadrant) |
| المصدر: | https://tel.archives-ouvertes.fr/tel-01921702 ; Micro et nanotechnologies/Microélectronique. Communauté Université Grenoble Alpes, 2018. Français. |
| بيانات النشر: | HAL CCSD |
| سنة النشر: | 2018 |
| المجموعة: | Archive ouverte HAL (Hyper Article en Ligne, CCSD - Centre pour la Communication Scientifique Directe) |
| مصطلحات موضوعية: | Nanowire, Reliability, Hot Carriers, Microelectronics, Microélectronique, Porteurs chauds, Trigate, Nanofil, Fiabilité, BTI, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics |
| الوصف: | By continuing to follow Moore’s law, transistors have reached ever smaller dimensions. However, from 100nm gate length, parasitic effects called short channel effects appear. As a result new architectures named trigate, nanowires or finfets have been developed. The transition from planar technology used for the last fifty years to 3D devices is a major technological breakthrough. The special features of these architectures like conduction over various crystalline planes, corner effects or carrier confinement effects raise numerous questions about their reliability. Main reliability mechanisms have to be study in order to evaluate 3D transistor aging. In this way, MOS transistor evolution and planar architecture limits have first been reminded. The electrical degradation mechanisms and their characterization methods have also been exposed. As oxide defects represent an important part of device reliability, impact on threshold voltage VT of an elementary charge q has been simulated in accordance to its spatial localization. Thus we can notice that the defect influence on VT change with at once its position and the device dimensions. Next, this manuscript focuses on Bias Temperature Instabilities (BTI). A parallel has been done between narrow Trigate devices and wide ones which can be considered as planar transistors and a width effect on NBTI (Negative BTI) degradation has been highlighted. Another major reliability mechanism is called hot carrier degradation. Its principle models developed on planar architecture have been remembered and their validity on Trigate transistors has been verified. During HC stress, current density can be so high that self-heating effects appear and degrade device electrical parameters. Therefore this contribution has been decorrelate from HC degradation in order to obtain the result of HC stress only. As in BTI chapter, width effect has also been evaluated for this reliability mechanism. Finally strain effects in channel region have been analyzed from both performance and reliability ... |
| نوع الوثيقة: | doctoral or postdoctoral thesis |
| اللغة: | French |
| Relation: | tel-01921702; https://tel.archives-ouvertes.fr/tel-01921702; https://tel.archives-ouvertes.fr/tel-01921702/document; https://tel.archives-ouvertes.fr/tel-01921702/file/Manuscript_final_corrig%C3%A9.pdf |
| الاتاحة: | https://tel.archives-ouvertes.fr/tel-01921702 https://tel.archives-ouvertes.fr/tel-01921702/document https://tel.archives-ouvertes.fr/tel-01921702/file/Manuscript_final_corrig%C3%A9.pdf |
| Rights: | info:eu-repo/semantics/OpenAccess |
| رقم الانضمام: | edsbas.4481019C |
| قاعدة البيانات: | BASE |
| الوصف غير متاح. |