Report
Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
العنوان: | Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing |
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المؤلفون: | Khadem, Alireza, Fujiki, Daichi, Chen, Hilbert, Gu, Yufeng, Talati, Nishil, Mahlke, Scott, Das, Reetuparna |
سنة النشر: | 2025 |
المجموعة: | Computer Science |
مصطلحات موضوعية: | Computer Science - Hardware Architecture |
الوصف: | In-cache computing technology transforms existing caches into long-vector compute units and offers low-cost alternatives to building expensive vector engines for mobile CPUs. Unfortunately, existing long-vector Instruction Set Architecture (ISA) extensions, such as RISC-V Vector Extension (RVV) and Arm Scalable Vector Extension (SVE), provide only one-dimensional strided and random memory accesses. While this is sufficient for typical vector engines, it fails to effectively utilize the large Single Instruction, Multiple Data (SIMD) widths of in-cache vector engines. This is because mobile data-parallel kernels expose limited parallelism across a single dimension. Based on our analysis of mobile vector kernels, we introduce a long-vector Multi-dimensional Vector ISA Extension (MVE) for mobile in-cache computing. MVE achieves high SIMD resource utilization and enables flexible programming by abstracting cache geometry and data layout. The proposed ISA features multi-dimensional strided and random memory accesses and efficient dimension-level masked execution to encode parallelism across multiple dimensions. Using a wide range of data-parallel mobile workloads, we demonstrate that MVE offers significant performance and energy reduction benefits of 2.9x and 8.8x, on average, compared to the SIMD units of a commercial mobile processor, at an area overhead of 3.6%. Comment: 2025 IEEE International Symposium on High-Performance Computer Architecture (HPCA) |
نوع الوثيقة: | Working Paper |
URL الوصول: | http://arxiv.org/abs/2501.09902 |
رقم الانضمام: | edsarx.2501.09902 |
قاعدة البيانات: | arXiv |
الوصف غير متاح. |