ChronoSym: a new approach for fast and accurate SoC cosimulation
| العنوان: | ChronoSym: a new approach for fast and accurate SoC cosimulation |
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| المؤلفون: | Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya, Iuliana Bacivarov |
| المساهمون: | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Torella, Lucie |
| المصدر: | International Journal of Embedded Systems International Journal of Embedded Systems, Inderscience, 2005, Volume: 1-Issue: 1/2, pp.103-111 |
| بيانات النشر: | Inderscience Publishers, 2005. |
| سنة النشر: | 2005 |
| مصطلحات موضوعية: | hardware-software cosimulation, Computer science, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 02 engineering and technology, 01 natural sciences, Instruction set, system-on-chip, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, SOC design, timing accuracy, 020202 computer hardware & architecture, HAL simulation model, Computer architecture, SOC verification, timed native execution, Hardware and Architecture, PACS 85.42, Embedded system, Key (cryptography), embedded systems, Design cycle, business, SoC validation, Software |
| الوصف: | The early validation of modern SoC is not anymore feasible using traditional cycle-accurate cosimulations. These are based on the concurrent execution between SW running on multiple Instruction Set Simulators and HW simulators. The challenge is then speeding-up the simulation, without sacrificing the accuracy of traditional methods. The key contribution of this paper is a novel fast and accurate HW/SW cosimulation approach, allowing to handle large SoCs, while reducing the design cycle. The key underlying concepts are timed native SW execution, combined with detailed HW/SW interaction models. This approach is implemented in ChronoSym tool and applied to two real SoC applications. |
| تدمد: | 1741-1076 1741-1068 |
| DOI: | 10.1504/ijes.2005.008812 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c5c767e2b6f798d8ac7ee8123c2c9d92 https://doi.org/10.1504/ijes.2005.008812 |
| رقم الانضمام: | edsair.doi.dedup.....c5c767e2b6f798d8ac7ee8123c2c9d92 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 17411076 17411068 |
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| DOI: | 10.1504/ijes.2005.008812 |