A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
| العنوان: | A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links |
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| المؤلفون: | Juergen Schloeffel, Cristiano Santos, Alexandre Arriordaz, Lee Wang, Yvain Thonnart, Christian Bernard, Eric Flamand, Abbas Sheibanyrad, Frédéric Pétrot, Fabien Clermidy, S. Cheramy, Edith Beigne, Romain Lemaire, Denis Dutoit, Pascal Vivet, Didier Lattard, Florian Darve, Ivan Miro-Panades, Jean Michailos |
| المساهمون: | Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Mentor Graphics, ANR-10-AIRT-0005,NANOELEC,NANOELEC(2010), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), ANR: ANR-10-AIRT-05,Programme Investissements d’Avenir |
| المصدر: | IEEE Journal of Solid-State Circuits IEEE Journal of Solid-State Circuits, 2016, 52 (1), pp.33-49. ⟨10.1109/JSSC.2016.2611497⟩ IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, 2016, 52 (1), pp.33-49. ⟨10.1109/JSSC.2016.2611497⟩ |
| بيانات النشر: | HAL CCSD, 2016. |
| سنة النشر: | 2016 |
| مصطلحات موضوعية: | Engineering, Multi-core processor, Through-silicon via, business.industry, 020208 electrical & electronic engineering, Fault tolerance, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Supercomputer, 7. Clean energy, Die (integrated circuit), 020202 computer hardware & architecture, [SPI]Engineering Sciences [physics], Asynchronous communication, Scalability, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [INFO]Computer Science [cs], Electrical and Electronic Engineering, business, Asynchronous circuit |
| الوصف: | International audience; Future many cores, either for high performance computing or for embedded applications, are facing the powerwall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through siliconvia (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipationdevoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, interms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eightdie layers. |
| اللغة: | English |
| تدمد: | 0018-9200 |
| DOI: | 10.1109/JSSC.2016.2611497⟩ |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_dedup___::74c17aea1b2ae9d9edf7df966c526039 https://hal.sorbonne-universite.fr/hal-01447433 |
| Rights: | CLOSED |
| رقم الانضمام: | edsair.doi.dedup.....74c17aea1b2ae9d9edf7df966c526039 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 00189200 |
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| DOI: | 10.1109/JSSC.2016.2611497⟩ |